785ecf0991
According to RM0041.pdf clock tree for stm32f100xx devices is different from both STM32F10X density and connectivity lines devices, but is a combination of both. Rework symbols definitions so that STM32F100xx is neither of those and uses: - CLOCK_STM32_PLL_MULTIPLIER as on SOC_STM32F10X_DENSITY_DEVICE - CLOCK_STM32_PLL_PREDIV1 as on SOC_STM32F10X_CONNECTIVITY_LINE_... Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
34 lines
981 B
Plaintext
34 lines
981 B
Plaintext
# STM32F1 PLL configuration options
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# Copyright (c) 2019 Linaro
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_STM32F1X
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config CLOCK_STM32_PLL_XTPRE
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bool "HSE to PLL /2 prescaler"
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depends on SOC_STM32F10X_DENSITY_DEVICE && CLOCK_STM32_PLL_SRC_HSE
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help
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Enable this option to enable /2 prescaler on HSE to PLL clock signal
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config CLOCK_STM32_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 9
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range 2 16 if !SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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range 4 9 if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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help
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PLL multiplier, PLL output must not exceed 72MHz. Allowed values:
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Density devices: 2-16
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Connectivity devices: 4 - 9 and 13 ( used for multiplication factor 6.5).
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config CLOCK_STM32_PLL_PREDIV1
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int "PREDIV1 Prescaler"
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depends on !SOC_STM32F10X_DENSITY_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 1
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range 1 16
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help
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PREDIV1 is PLL clock signal prescaler, allowed values: 1 - 16.
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endif # SOC_SERIES_STM32F1X
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