zephyr/arch/riscv/core
Wolfgang Reißnegger 535fc38fe7 riscv: Don't reschedule on back-to-back interrupts
In some cases the 'reschedule' code path is executed when the current
thread is the same as the next thread in the ready Q. If this happens,
the swap_return_value of the thread is ifalsely being reset to -EAGAIN.

This commit prevents the rescheduling code to run if the current thread
is the same as the thread in the ready Q.

Signed-off-by: Wolfgang Reißnegger <gnagflow@fb.com>
2021-09-03 12:20:03 -04:00
..
offsets arch: riscv: remove unneeded context switch to gp register 2021-08-18 05:18:55 -04:00
pmp linker: align _image_rodata and _image_rom start/end/size linker symbols 2021-08-28 08:48:03 -04:00
CMakeLists.txt arch: riscv: add common stub reboot function 2021-03-04 11:09:51 -06:00
cpu_idle.c
fatal.c arch: riscv: remove unneeded context switch to gp register 2021-08-18 05:18:55 -04:00
irq_manage.c kernel: Cleanup logger setup in kernel files 2020-11-27 09:56:34 -05:00
irq_offload.c
isr.S riscv: Don't reschedule on back-to-back interrupts 2021-09-03 12:20:03 -04:00
prep_c.c arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
reboot.c arch: riscv: add common stub reboot function 2021-03-04 11:09:51 -06:00
reset.S arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00
swap.S
thread.c Revert "arch: riscv: added support for custom initialization of gp register" 2021-08-18 05:18:55 -04:00
tls.c riscv: add support for thread local storage 2020-10-24 10:52:00 -07:00
userspace.S arch: riscv: add memory protection support 2020-11-09 15:37:11 -05:00