zephyr/soc
Dino Li 29d039335f cleanup: soc: it8xxx2: remove unnecessary code
Code removed:
- IT8XXX2 doesn't support soc level software interrupt hence remove
  them.
- To use common macro to access csr (control status register).
- To remove CONFIG_RISCV_HAS_PLIC related code. IT8XXX2 uses its own
  interrupt controller code.
- To remove ite_write and ite_read. We don't use them anymore.

Code changed:
- Return true from arch_irq_is_enabled() when external interrupt-enable
  bit, and SOC's IER are both true.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-09-28 11:36:23 +02:00
..
arc boards: arc: add a nsim_hs_mpuv6 board simulator 2021-08-27 11:45:43 -04:00
arm soc: nrf53: Add missing HAS_HW_NRF_* entries 2021-09-28 11:30:09 +02:00
arm64 linker: align _image_text_start/end/size linker symbols name 2021-08-28 08:48:03 -04:00
nios2
posix posix: Add missing include 2021-04-27 13:17:36 -04:00
riscv cleanup: soc: it8xxx2: remove unnecessary code 2021-09-28 11:36:23 +02:00
sparc boards: set CPU_HAS_FPU on LEON3 soc and boards 2020-12-04 14:33:43 +02:00
x86 bluetooth: remove Kconfig options CONFIG_BT_*_ON_DEV_NAME 2021-08-25 18:05:17 -04:00
xtensa esp32s2: drivers: clock_control: add support 2021-09-27 22:02:08 -04:00
Kconfig kconfig: soc and shield cleanup 2021-06-11 16:13:22 +02:00