6a3309a9e4
STM32 Cortex-M33, such as the L5/H5/U5 series, have a cache peripheral for instruction and data caches, which are not present in the C-M33 architecture spec. The driver defaults to direct mapped cache as it uses less power than the alternative set associative mapping [1]. This has also been the default in stm32 soc initialization code for chips that have the ICACHE peripheral, which makes it the safest choice for backward compatibility. The exception to the rule is STM32L5, which has the n-way cache mode selected in SOC code. [1]: https://en.wikipedia.org/wiki/Cache_placement_policies Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com> |
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| .. | ||
| cache_andes_l2.h | ||
| cache_andes.c | ||
| cache_aspeed.c | ||
| cache_handlers.c | ||
| cache_nrf.c | ||
| cache_nxp_xcache.c | ||
| cache_stm32.c | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.andes | ||
| Kconfig.aspeed | ||
| Kconfig.nrf | ||
| Kconfig.nxp_xcache | ||
| Kconfig.stm32 | ||