Jakub Zymelka 9473e3236d dts: nordic: Align boards dts to new VEVIF, BELLBOARD nomenclature ... After changing the VEVIF and BELLBOARD names, the dts for the individual boards must be aligned. Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>		2024-06-15 04:41:47 -04:00
..
andes	dts: bindings: add andestech,l2c	2024-04-22 09:19:27 -04:00
efinix	dts/riscv/efinix: add the efinix,vexriscv-sapphire compatible string	2024-01-31 10:41:49 +01:00
espressif	soc: esp32c6: Kconfig and .ld updates, DTS and comments fix	2024-06-14 18:51:46 -04:00
gd	dts/riscv: add riscv compatible string where it's missing	2024-01-31 10:41:49 +01:00
ite	drivers: pinctrl: ITE: Add a property configure pin current strength	2024-06-06 00:41:35 -07:00
lowrisc	dts: opentitan: update plic interrupt count to match spec	2024-03-22 09:23:46 +00:00
microchip	dts: mbox: add PolarFire SoC mailbox interface	2024-02-01 04:33:16 -05:00
niosv	dts/riscv: add riscv compatible string where it's missing	2024-01-31 10:41:49 +01:00
nordic	dts: nordic: Align boards dts to new VEVIF, BELLBOARD nomenclature	2024-06-15 04:41:47 -04:00
openisa	Bluetooth: controller: Update to new HCI driver API	2024-06-11 19:42:49 -04:00
qemu	dts: set the riscv,isa property for virt-based targets	2024-05-15 09:30:23 +02:00
sifive	dts: sifive: Update SoC compats	2024-04-18 14:56:00 +02:00
starfive	dts: jh7110: fix memory definitions	2024-04-09 14:20:39 +02:00
telink
neorv32.dtsi	dts/riscv: add riscv compatible string where it's missing	2024-01-31 10:41:49 +01:00
renode_riscv32_virt.dtsi	dts: riscv: add a SoC dtsi for Renode RISC-V Virt SoC	2024-01-08 12:35:10 +01:00
riscv32-litex-vexriscv.dtsi	soc: riscv: litex: add reboot	2024-06-06 15:46:40 +01:00