c1a462e1a5
There actually is no triple faults on Xtensa. Once PS.EXCM is set, it keeps going through double exception vector for any new exceptions. However, our exception code needs to unmask PS.EXCM to enable register window operations. So after that, any new exceptions will go through the kernel or user vectors depending on PS.UM. If there is continuous faults, it may keep ping-ponging between double and kernel/user exception vectors that may never get resolved. Since we stash DEPC during double exception, and the stashed one is only cleared once the double exception has been processed, we can use the stashed DEPC value to detect if the next exception could be considered a triple fault. If such a case exists, simply jump to an infinite loop, or quit the simulator, or invoke debugger. Signed-off-by: Daniel Leung <daniel.leung@intel.com> |
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| .. | ||
| arc | ||
| arm | ||
| arm64 | ||
| common | ||
| mips | ||
| nios2 | ||
| posix | ||
| riscv | ||
| sparc | ||
| x86 | ||
| xtensa | ||
| archs.yml | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.v1 | ||
| Kconfig.v2 | ||