43856f2dc6
The cycle64 sample is intended to complement `test_clock_cycle_64()` in `tests/kernel/common`. The sample demonstrates the upper 32-bits of the 64-bit cycle counter incrementing when the bottom 32-bits roll over from `UINT32_MAX` to 0. If the upper 32-bits of the 64-bit cycle counter does not increment, then an error message is printed. ``` west build -p auto -b qemu_cortex_a53 -t run \ samples/kernel/cycle64 ... *** Booting Zephyr OS build v2.7.99-1124-gd7ba4e394832 *** wrap-around should occur in 68s [ddd:hh:mm:ss.0ms] [000:00:00:00.020]: c64: 0000000000174258 [000:00:01:08.760]: c64: 000000010027f8bb [000:00:02:17.490]: c64: 0000000200348c85 ``` Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
78 lines
1.3 KiB
C
78 lines
1.3 KiB
C
/*
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* Copyright (c) 2021 Friedt Professional Engineering Services, Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr.h>
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static void swap64(uint64_t *a, uint64_t *b)
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{
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uint64_t t = *a;
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*a = *b;
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*b = t;
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}
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static void msg(uint64_t c64)
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{
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int64_t ms = k_uptime_get();
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int s = ms / 1000;
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int m = s / 60;
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int h = m / 60;
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int d = h / 24;
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h %= 24;
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m %= 60;
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s %= 60;
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ms %= 1000;
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printk("[%03d:%02d:%02d:%02d.%03d]: cycle: %016" PRIx64 "\n", d, h, m, s, (int)ms, c64);
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}
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uint32_t timeout(uint64_t prev, uint64_t now)
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{
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uint64_t next = prev + BIT64(32) - now;
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next &= UINT32_MAX;
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if (next == 0) {
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next = UINT32_MAX;
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}
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return (uint32_t)next;
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}
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void main(void)
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{
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enum {
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CURR,
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PREV,
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};
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int i;
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uint64_t now;
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uint64_t c64[2];
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printk("wrap-around should occur in %us\n",
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(uint32_t)(BIT64(32) / (uint32_t)sys_clock_hw_cycles_per_sec()));
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printk("[ddd:hh:mm:ss.0ms]\n");
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c64[CURR] = k_cycle_get_64();
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msg(c64[CURR]);
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for (i = 0; i < 3; ++i) {
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k_sleep(Z_TIMEOUT_CYC(timeout(c64[CURR], k_cycle_get_64())));
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now = k_cycle_get_64();
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swap64(&c64[PREV], &c64[CURR]);
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c64[CURR] = now;
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msg(c64[CURR]);
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__ASSERT(((c64[CURR] - c64[PREV]) >> 32) == 1,
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"The 64-bit cycle counter did not increment!");
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}
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printk("SUCCESS\n");
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}
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