a737999b5b
This implements support for the optional Interrupt Translation Service (ITS) module of the GICv3 Interrupt Controller. The current implementation is designed for MSI/MSI-X interrupt delivery in mind. The gicv3 driver calls each ITS INVALL command when LPI interrupts are enabled/disabled. A simple atomic integer is used to allocate unique LPI INTIDs to ITS users. CPUs numbers are directly mapped as ICIDs into the Collections Table. As a limitation it doesn't support indirect Device table to simplify implementation but may use a large amount of memory. INV, DISCARD, MOVI and MOVALL commands are not implemented. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
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| .. | ||
| CMakeLists.txt | ||
| intc_arcv2_irq_unit.c | ||
| intc_cavs.c | ||
| intc_cavs.h | ||
| intc_dw.c | ||
| intc_dw.h | ||
| intc_esp32.c | ||
| intc_exti_stm32.c | ||
| intc_gic_common_priv.h | ||
| intc_gic.c | ||
| intc_gicv3_its.c | ||
| intc_gicv3_priv.h | ||
| intc_gicv3.c | ||
| intc_intel_vtd.c | ||
| intc_intel_vtd.h | ||
| intc_ioapic_priv.h | ||
| intc_ioapic.c | ||
| intc_irqmp.c | ||
| intc_ite_it8xxx2.c | ||
| intc_ite_it8xxx2.h | ||
| intc_loapic_spurious.S | ||
| intc_loapic.c | ||
| intc_mchp_ecia_xec.c | ||
| intc_miwu.c | ||
| intc_plic.c | ||
| intc_rv32m1_intmux.c | ||
| intc_sam0_eic_priv.h | ||
| intc_sam0_eic.c | ||
| intc_shared_irq.c | ||
| intc_swerv_pic.c | ||
| intc_system_apic.c | ||
| intc_vexriscv_litex.c | ||
| Kconfig | ||
| Kconfig.cavs | ||
| Kconfig.dw | ||
| Kconfig.esp32 | ||
| Kconfig.gic | ||
| Kconfig.intel_vtd | ||
| Kconfig.it8xxx2 | ||
| Kconfig.loapic | ||
| Kconfig.multilevel | ||
| Kconfig.multilevel.aggregator_template | ||
| Kconfig.npcx | ||
| Kconfig.rv32m1 | ||
| Kconfig.sam0 | ||
| Kconfig.shared_irq | ||
| Kconfig.stm32 | ||
| Kconfig.xec | ||