1204aa25c8
the FIFO Rx need to have a Minimum memory to works distributed the rest of the ram_size memory between the different TX FIFOs except the first which is a control endtype with max data payload of 64 bytes Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com> |
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| .. | ||
| bc12 | ||
| common | ||
| device | ||
| udc | ||
| uhc | ||
| uvb | ||
| CMakeLists.txt | ||
| Kconfig | ||