zephyr/include/arch
Andy Ross 77719b81e9 arch/xtensa: Clean up fatal error handling
Update the xtensa backend to work better with the new fatal error
architecture.  Move the stack frame dump (xtensa uses a variable-size
frame becuase we don't spill unused register windows, so it doesn't
strictly have an ESF struct) into z_xtensa_fatal_error().  Unify the
older exception logging with the newer one (they'd been sort of glomed
together in the recent rework), mostly using the asm2 code but with
the exception cause stringification and the PS register field
extraction from the older one.

Note that one shortcoming is that the way the dispatch code works, we
don't have access to the spilled frame from within the spurious error
handler, so this can't log the interrupted CPU state.  This isn't
fixable easily without adding overhead to every interrupt entry, so it
needs to stay the way it is for now.  Longer term we could exract the
caller frame from the window state and figure it out with some
elaborate assembly, I guess.

Fixes #18140

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-08-22 17:57:40 -04:00
..
arc arc: rearrange for standard use of extern "C" 2019-08-20 00:49:15 +02:00
arm arch/arm: rearrange for standard use of extern "C" 2019-08-20 00:49:15 +02:00
common arch/common: rearrange for standard use of extern "C" 2019-08-20 00:49:15 +02:00
nios2 arch/nios2: rearrange for standard use of extern "C" 2019-08-20 00:49:15 +02:00
posix POSIX arch: Fixe issues related to extern "C" 2019-08-12 15:10:15 +02:00
riscv arch/riscv: rearrange for standard use of extern "C" 2019-08-18 16:20:10 +02:00
x86 arch/x86: rearrange for standard use of extern "C" 2019-08-20 00:49:15 +02:00
x86_64 kernel: rename NANO_ESF 2019-07-25 15:06:58 -07:00
xtensa arch/xtensa: Clean up fatal error handling 2019-08-22 17:57:40 -04:00
cpu.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
syscall.h arch/x86: move arch/x86/syscall.h to arch/x86/ia32/syscall.h 2019-07-02 19:30:00 -04:00