zephyr/include/arch/riscv
Nicolas Pitre c8bfc2afda riscv: make arch_is_user_context() SMP compatible
This is painful. There is no way for u-mode code to know if we're
currently executing in u-mode without generating a fault, besides
stealing a general purpose register away from the standard ABI
that is. And a global variable doesn't work on SMP as this must be
per-CPU and we could be migrated to another CPU just at the right
moment to peek at the wrong CPU variable (and u-mode can't disable
preemption either).

So, given that we'll have to pay the price of an exception entry
anyway, let's at least make it free to privileged threads by using
the mscratch register as the non-user context indicator (it must
be zero in m-mode for exception entry to work properly). In the
case of u-mode we'll simulate a proper return value in the
exception trap code. Let's settle on the return value in t0
and omit the volatile to give the compiler a chance to cache
the result.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-03-21 07:28:05 -04:00
..
common everywhere: fix typos 2022-03-14 20:22:24 -04:00
riscv-privilege
arch_inlines.h arch/riscv: Implement arch_curr_cpu() 2022-02-25 19:13:50 -05:00
arch.h riscv: better abstraction for register-wide FP load/store opcodes 2022-03-21 07:28:05 -04:00
csr.h copyright: add missing license 2021-09-24 17:07:37 -04:00
error.h riscv: exception code mega simplification and optimization 2022-03-21 07:28:05 -04:00
exp.h riscv: isr.S: dedicate a register to &current_cpu 2022-03-21 07:28:05 -04:00
syscall.h riscv: make arch_is_user_context() SMP compatible 2022-03-21 07:28:05 -04:00
thread.h riscv: implement arch_switch() 2022-03-21 07:28:05 -04:00