zephyr/arch/arc/core
Carlo Caione f000695243 cache: Rename sys_{dcache,icache}_* to sys_{data,instr}_cache_*
To have a common prefix.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-05-08 07:00:33 +02:00
..
mpu arch: arc: Fix 10.4 violations 2021-04-10 09:59:37 -04:00
offsets ARC: allow to build code for processors without ZOL 2021-05-07 14:55:49 -05:00
secureshield
arc_connect.c
arc_smp.c arch: arc: Fix 10.4 violations 2021-04-10 09:59:37 -04:00
cache.c cache: Rename sys_{dcache,icache}_* to sys_{data,instr}_cache_* 2021-05-08 07:00:33 +02:00
CMakeLists.txt
cpu_idle.S ARC: rewrite ASM code with asm-compat macroses 2021-05-07 14:55:49 -05:00
fast_irq.S
fatal.c ARC: allow to build code for processors without ZOL 2021-05-07 14:55:49 -05:00
fault_s.S ARC: rewrite ASM code with asm-compat macroses 2021-05-07 14:55:49 -05:00
fault.c
irq_manage.c
irq_offload.c
isr_wrapper.S ARC: mark accesses which are 32 bit despite of platform bittnes 2021-05-07 14:55:49 -05:00
prep_c.c ARC: cleanup instruction cache initialization 2021-03-12 18:29:07 -05:00
regular_irq.S ARC: allow to build code for processors without ZOL 2021-05-07 14:55:49 -05:00
reset.S ARC: rewrite ASM code with asm-compat macroses 2021-05-07 14:55:49 -05:00
switch.S ARC: mark accesses which are 32 bit despite of platform bittnes 2021-05-07 14:55:49 -05:00
thread_entry_wrapper.S ARC: rewrite ASM code with asm-compat macroses 2021-05-07 14:55:49 -05:00
thread.c ARC: add TLS support for ARCv3 2021-05-07 14:55:49 -05:00
timestamp.c clocks: rename z_tick_get -> sys_clock_tick_get 2021-03-19 11:22:17 -04:00
tls.c
userspace.S
vector_table.c ARC: make vector table bit agnostic 2021-05-07 14:55:49 -05:00
vector_table.ld