Andrew Boie 51e3c9efa5 x86: reserve the first megabyte ... A more comprehensive solution would use E820 enumeration, but we are unlikely to ever care that much, as we intend to use demand paging on microcontrollers and not PC-like hardware. This is really to just prevent QEMU from crashing. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>		2021-01-21 16:47:00 -05:00
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arc	cache: Rename CACHE_FLUSHING to CACHE_MANAGEMENT	2021-01-19 14:31:02 -05:00
arm	soc: arm: nxp_imx: rt: mimxrt1024: add device support	2021-01-21 14:50:45 -05:00
nios2	soc: nios2: Cleanup linker scripts to use new DTS macros	2020-04-30 20:59:13 -05:00
posix	posix: Add cpu_hold() function to better emulate code delay	2020-12-14 12:32:11 +01:00
riscv	soc/riscv: add the QEMU "RISC-V VirtIO board"	2021-01-15 13:06:33 -05:00
sparc	boards: set CPU_HAS_FPU on LEON3 soc and boards	2020-12-04 14:33:43 +02:00
x86	x86: reserve the first megabyte	2021-01-21 16:47:00 -05:00
xtensa	tests: common: fix kernel.common test case build fail in intel_adsp_cavs	2021-01-21 14:47:31 -05:00
Kconfig	timing: introduce timing functions as a generic feature	2020-09-05 13:28:38 -05:00