f7fffae8aa
Change all the Intel and Wind River code license from BSD-3 to Apache 2. Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Allan Stephens <allan.stephens@windriver.com> Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
141 lines
3.3 KiB
C
141 lines
3.3 KiB
C
/* irq-test-common.h - IRQ utilities for tests */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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DESCRIPTION
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Interrupt stuff, abstracted across CPU architectures.
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*/
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#ifndef _IRQ_TEST_COMMON__H_
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#define _IRQ_TEST_COMMON__H_
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#if defined(CONFIG_X86_32)
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#define IRQ_PRIORITY 3
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEX_M)
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#define IRQ_PRIORITY _EXC_PRIO(3)
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif
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/*
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* NUM_SW_IRQS must be defined before this file is included, and it
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* currently only supports 1 or 2 as valid values.
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*/
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#if !defined(NUM_SW_IRQS)
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#error NUM_SW_IRQS must be defined before including irq-test-common.h
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#elif NUM_SW_IRQS < 1 || NUM_SW_IRQS > 2
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#error NUM_SW_IRQS only supports 1 or 2 IRQs
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#endif
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typedef void (*vvfn)(void); /* void-void function pointer */
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typedef void (*vvpfn)(void *); /* void-void_pointer function pointer */
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#if defined(CONFIG_X86_32)
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/*
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* Opcode for generating a software interrupt. The ISR associated with each
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* of these software interrupts will call either nano_isr_lifo_put() or
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* nano_isr_lifo_get(). The imm8 data in the opcode sequence will need to be
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* filled in after calling irq_connect().
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*/
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static char sw_isr_trigger_0[] = {
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0xcd, /* OPCODE: INT imm8 */
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0x00, /* imm8 data (vector to trigger) filled in at runtime */
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0xc3 /* OPCODE: RET (near) */
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};
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#if NUM_SW_IRQS >= 2
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static char sw_isr_trigger_1[] = {
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/* same as above */
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0xcd,
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0x00,
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0xc3
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};
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#endif /* NUM_SW_IRQS >= 2 */
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <nanokernel.h>
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static inline void sw_isr_trigger_0(void)
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{
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_NvicSwInterruptTrigger(0);
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}
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#if NUM_SW_IRQS >= 2
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static inline void sw_isr_trigger_1(void)
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{
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_NvicSwInterruptTrigger(1);
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}
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif
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struct isrInitInfo {
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vvpfn isr[2];
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void *arg[2];
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};
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/**
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*
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* @brief Init interrupts
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*
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*/
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static int initIRQ(struct isrInitInfo *i)
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{
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#if defined(CONFIG_X86_32)
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int vector; /* vector to which interrupt is connected */
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if (i->isr[0]) {
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vector = irq_connect(NANO_SOFT_IRQ, IRQ_PRIORITY, i->isr[0],
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i->arg[0]);
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if (-1 == vector) {
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return -1;
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}
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sw_isr_trigger_0[1] = vector;
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}
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#if NUM_SW_IRQS >= 2
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if (i->isr[1]) {
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vector = irq_connect(NANO_SOFT_IRQ, IRQ_PRIORITY, i->isr[1],
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i->arg[1]);
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if (-1 == vector) {
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return -1;
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}
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sw_isr_trigger_1[1] = vector;
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}
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#endif /* NUM_SW_IRQS >= 2 */
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEX_M)
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if (i->isr[0]) {
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(void) irq_connect(0, IRQ_PRIORITY, i->isr[0], i->arg[0]);
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irq_enable(0);
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}
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if (i->isr[1]) {
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(void) irq_connect(1, IRQ_PRIORITY, i->isr[1], i->arg[1]);
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irq_enable(1);
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}
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif /* CONFIG_X86_32 */
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return 0;
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}
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#endif /* _IRQ_TEST_COMMON__H_ */
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