zephyr/drivers/ethernet/phy
Robert Hancock 3a0f26f02a drivers: ethernet: vsc8541: add RGMII clock delay configuration
As the code noted, the RGMII RX and TX clock delay values may need to
change depending on the MAC configuration or the PCB layout. Add
properties to allow configuring these in the device tree, defaulting to
the previous hard-coded values if not present.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
2025-05-05 21:57:05 +02:00
..
CMakeLists.txt drivers: ethernet: phy: add zephyr-keep-sorted-start 2025-03-19 17:16:17 +01:00
Kconfig drivers: ethernet: Add TI DP83867 eth phy driver 2025-03-07 19:51:02 +01:00
Kconfig.dm8806
Kconfig.microchip_t1s
Kconfig.tja1103
phy_adin2111_priv.h
phy_adin2111.c drivers: ethernet: phy: rename LINK_*_*BASE_T 2025-04-28 09:22:09 +01:00
phy_dm8806_priv.h
phy_dm8806.c drivers: ethernet: phy: rename LINK_*_*BASE_T 2025-04-28 09:22:09 +01:00
phy_microchip_ksz8081.c drivers: ethernet: phy: rename LINK_*_*BASE_T 2025-04-28 09:22:09 +01:00
phy_microchip_t1s.c drivers: ethernet: phy: rename LINK_*_*BASE_T 2025-04-28 09:22:09 +01:00
phy_microchip_vsc8541.c drivers: ethernet: vsc8541: add RGMII clock delay configuration 2025-05-05 21:57:05 +02:00
phy_mii.c drivers: ethernet: phy: rename LINK_*_*BASE_T 2025-04-28 09:22:09 +01:00
phy_oa_tc14_plca.c
phy_qualcomm_ar8031.c drivers: ethernet: phy: rename LINK_*_*BASE_T 2025-04-28 09:22:09 +01:00
phy_realtek_rtl8211f.c drivers: ethernet: phy: rename LINK_*_*BASE_T 2025-04-28 09:22:09 +01:00
phy_ti_dp83825.c drivers: ethernet: phy: rename LINK_*_*BASE_T 2025-04-28 09:22:09 +01:00
phy_ti_dp83867.c drivers: ethernet: phy: rename LINK_*_*BASE_T 2025-04-28 09:22:09 +01:00
phy_tja1103.c drivers: ethernet: phy: rename LINK_*_*BASE_T 2025-04-28 09:22:09 +01:00