zephyr/arch/xtensa/core
Anas Nashif 2aacbcaab5 style: add missing curly braces in if/while/for statements.
Add missing curly braces in if/while/for statements.

This is a style guideline we have that was not enforced in CI. All
issues fixed here were detected by sonarqube SCA.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-05-17 14:10:33 +02:00
..
offsets xtensa: userspace: swap page tables via assembly code 2025-04-17 00:57:19 +02:00
startup
CMakeLists.txt xtensa: update HAL path for custom compilations 2025-05-09 08:23:09 +02:00
coredump.c
cpu_idle.c
crt1.S
debug_helpers_asm.S
elf.c style: add missing curly braces in if/while/for statements. 2025-05-17 14:10:33 +02:00
fatal.c Revert "arch: deprecate _current" 2025-01-10 07:49:08 +01:00
gdbstub.c xtensa: gdbstub: fix stack calculation 2025-05-13 18:38:12 +01:00
gen_vectors.py
gen_zsr.py xtensa: no need for flush register if threads are pin only 2025-04-17 00:57:19 +02:00
irq_manage.c
irq_offload.c
mem_manage.c
mmu.c xtensa: userspace: pre-compute MMU registers at domain init 2025-04-17 00:57:19 +02:00
mpu.c
prep_c.c xtensa: no need for flush register if threads are pin only 2025-04-17 00:57:19 +02:00
ptables.c xtensa: userspace: swap page tables via assembly code 2025-04-17 00:57:19 +02:00
README_MMU.txt
README_WINDOWS.rst
smp.c
syscall_helper.c xtensa: userspace: workaround return PC calc with loops 2025-04-17 00:57:19 +02:00
thread.c xtensa: userspace: prevent potential privilege escalation 2025-04-17 00:57:19 +02:00
timing.c
tls.c
userspace.S xtensa: userspace: use ADDX4 to calculate syscall table index 2025-04-17 00:57:19 +02:00
vector_handlers.c Revert "arch: deprecate _current" 2025-01-10 07:49:08 +01:00
window_vectors.S
xcc_stubs.c
xtensa_asm2_util.S xtensa: userspace: swap page tables via assembly code 2025-04-17 00:57:19 +02:00
xtensa_backtrace.c
xtensa_hifi.S
xtensa_intgen.py
xtensa_intgen.tmpl