f1f63dda17
This adds FPU sharing support with a lazy context switching algorithm. Every thread is allowed to use FPU/SIMD registers. In fact, the compiler may insert FPU reg accesses in anycontext to optimize even non-FP code unless the -mgeneral-regs-only compiler flag is used, but Zephyr currently doesn't support such a build. It is therefore possible to do FP access in IRS as well with this patch although IRQs are then disabled to prevent nested IRQs in such cases. Because the thread object grows in size, some tests have to be adjusted. Signed-off-by: Nicolas Pitre <npitre@baylibre.com> |
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| .. | ||
| atomic.rst | ||
| cpu_idle.rst | ||
| cxx_support.rst | ||
| fatal.rst | ||
| float.rst | ||
| interrupts.rst | ||
| polling.rst | ||
| version.rst | ||