0af51b072c
We've reversed core launch order to workaround issue of ARConnect initialization interfere with secondary cores startup (we don't want to workaround it in runtime as it's only possible in case of debug session). However it bring us new issues with the simulation run: - mismatch arcnum (core ID) with ARConnect ID - mismatch arcnum (core ID) with CPU name in nSIM instruction traces To avoid these issues let's use direct core order for simulation runs. Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> |
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| .. | ||
| __init__.py | ||
| blackmagicprobe.py | ||
| bossac.py | ||
| canopen_program.py | ||
| core.py | ||
| dediprog.py | ||
| dfu.py | ||
| esp32.py | ||
| ezflashcli.py | ||
| gd32isp.py | ||
| hifive1.py | ||
| intel_adsp.py | ||
| intel_cyclonev.py | ||
| jlink.py | ||
| linkserver.py | ||
| mdb.py | ||
| misc.py | ||
| native.py | ||
| nios2.py | ||
| nrf_common.py | ||
| nrfjprog.py | ||
| nrfutil.py | ||
| nsim.py | ||
| nxp_s32dbg.py | ||
| openocd.py | ||
| pyocd.py | ||
| qemu.py | ||
| silabs_commander.py | ||
| spi_burn.py | ||
| stm32cubeprogrammer.py | ||
| stm32flash.py | ||
| teensy.py | ||
| trace32.py | ||
| uf2.py | ||
| xtensa.py | ||