f246d9540c
This patch updates ipc response procedure in power down function. New flow is only limited to the writs into two registers. We need to clear the IPCxIDD register in case if its contains any leftovers from a previous responce. And then write a response to the IPCxIDR. To prepare response we need to copy incoming request and then mark it as replay. New message with IPC Busy bit set is then send to host. The reason for this is a change in the behavior of the IPC driver compared to how it worked when this function was originaly implemented. The biggest difference are enabled interrupts in register IPCxCTL. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com> |
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| .. | ||
| esp32 | ||
| esp32_net | ||
| esp32s2 | ||
| intel_adsp | ||
| nxp_adsp | ||
| sample_controller | ||
| CMakeLists.txt | ||