8ac6f74a7d
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds support for the "sample_controller" SoC (used by qemu_xtensa) as demonstration. As Xtensa lacks a common linker script at the arch level, enabling it for each platform will be a piecemeal effort. This patch adds it to the `soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is set to be called "RAM", and hooks are inserted so that gen_relocate_app.py can add the relevant linker bits. Also, `tests/application_developent/code_relocation` was tweaked to support the qemu_xtensa platform. Basically, add the relevant linker script and ensure that relevant memory regions have their program header (PHDR) associated. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
30 lines
556 B
Plaintext
30 lines
556 B
Plaintext
/*
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* Copyright 2022 The Chromium OS Authors
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/linker/sections.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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#define SRAM2_ADDR (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2)
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#define RAM_SIZE2 (0x4000000)
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MEMORY
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{
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SRAM2 (wx) : ORIGIN = (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2), LENGTH = RAM_SIZE2
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}
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PHDRS
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{
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sram2_phdr PT_LOAD;
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}
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#define MPU_ALIGN(region_size) \
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. = ALIGN(4)
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#include <xtensa-sample-controller.ld>
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