The logic of clock initialization for i2c fast mode (FM) and fast
mode plus (FMP) is as follows:
1 compute how many system clock cycles for SCL to be low
2 compute how many system clock cycles for SCL to be high by
subtracting the low duration computed above from the SCL period
3 verify the high duration computed in 2 is larger than a minimum
The bug is that the step 3 for the FMP is compared with the
minimum value for FM, and causes it to fail.
The fix corrects the bug.
Signed-off-by: Hu Dou <hugh.dou@gmail.com>
25564f73dc