Nicolas Pitre 7f74825958 riscv: add a qemu_riscv64 board ... This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board. Memory is tight so a few tests had to be disabled due to the extra memory usage compared to qemu_riscv32. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2019-08-09 09:11:45 -05:00
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can/frame	tests: enable native_posix_64 testing	2019-07-16 10:41:11 -07:00
dfu	tests: enable native_posix_64 testing	2019-07-16 10:41:11 -07:00
fs	tests/subsys/fs/nvs: entry delete test	2019-08-08 11:07:48 +02:00
jwt	tests: remove redundant CONFIG_HW_STACK_PROTECTION=y setting	2019-07-01 12:54:20 -07:00
logging	riscv: add a qemu_riscv64 board	2019-08-09 09:11:45 -05:00
settings	tests/subsys/settings/fcb: add check for target compatibility	2019-08-08 08:47:44 -05:00
shell/shell_history	shell_history_test: make the test succeed on 64-bit targets	2019-07-04 07:24:56 -04:00
storage/flash_map	tests: enable native_posix_64 testing	2019-07-16 10:41:11 -07:00
usb	Revert "sys/util.h: helper macro to perform pointer difference"	2019-07-17 03:44:03 -04:00