zephyr/include/arch
Karsten Koenig f0d4bdfe3f include: arch: riscv: rename global macro
SR and LR were used as global names for load and store RISC-V assembler
operations, colliding with other uses such as SR for STATUS REGISTER in
some peripherals. Renamed them to a longer more specific name to avoid
the collision.

Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2019-08-17 11:48:02 +02:00
..
arc arch: arc: add initial support of ARC TEE 2019-08-10 17:45:22 +02:00
arm arch: arm: cortex_r: Add memory barriers for register accesses 2019-08-09 22:50:50 +02:00
common cleanup: include/: move sys_io.h to sys/sys_io.h 2019-06-27 22:55:49 -04:00
nios2 kernel: rename NANO_ESF 2019-07-25 15:06:58 -07:00
posix POSIX arch: Fixe issues related to extern "C" 2019-08-12 15:10:15 +02:00
riscv include: arch: riscv: rename global macro 2019-08-17 11:48:02 +02:00
x86 x86: generate page tables at runtime 2019-08-07 12:50:53 -07:00
x86_64 kernel: rename NANO_ESF 2019-07-25 15:06:58 -07:00
xtensa kernel: rename NANO_ESF 2019-07-25 15:06:58 -07:00
cpu.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
syscall.h arch/x86: move arch/x86/syscall.h to arch/x86/ia32/syscall.h 2019-07-02 19:30:00 -04:00