zephyr/arch
Karsten Koenig f0d4bdfe3f include: arch: riscv: rename global macro
SR and LR were used as global names for load and store RISC-V assembler
operations, colliding with other uses such as SR for STATUS REGISTER in
some peripherals. Renamed them to a longer more specific name to avoid
the collision.

Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2019-08-17 11:48:02 +02:00
..
arc arch: arc: fix a bug when CONFIG_SMP is enabled 2019-08-11 21:18:38 +02:00
arm arch: arm: Add Cortex-R5 support 2019-08-09 22:50:50 +02:00
common cleanup: include/: move misc/__assert.h to sys/__assert.h 2019-06-27 22:55:49 -04:00
nios2 kernel: rename NANO_ESF 2019-07-25 15:06:58 -07:00
posix POSIX arch: Fixe issues related to extern "C" 2019-08-12 15:10:15 +02:00
riscv include: arch: riscv: rename global macro 2019-08-17 11:48:02 +02:00
x86 x86: add build assert that RAM bounds <= 4GB 2019-08-07 12:50:53 -07:00
x86_64 kernel: rename NANO_ESF 2019-07-25 15:06:58 -07:00
xtensa xtensa: mask interrupts earlier 2019-08-14 10:11:05 -07:00
CMakeLists.txt license: cleanup: add SPDX Apache-2.0 license identifier 2019-04-07 08:45:22 -04:00
Kconfig riscv32: rename to riscv 2019-08-02 13:54:48 -07:00