7cbdb6c5c0
The newer series of timer drivers will compare counters vs. the last tick boundary to compute a number of ticks to announce to the kernel. In the case of CONFIG_TICKLESS=n, this actually represents a change of behavior from our old scheme where "ticks" always reflected the number of interrupts received. The distinction only matters when an interrupt is delayed more than a full tick, of course. But that actually makes a difference to some timekeeping code. Restore the old behavior. This also has the benefit of further reducing code size when !TICKLESS and improving performance of the ISR by removing the division (remember Cortex M0 has no hardware divide!). Fixes #12409 Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
153 lines
3.8 KiB
C
153 lines
3.8 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/system_timer.h>
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#include <sys_clock.h>
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#include <spinlock.h>
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#define HPET_REG32(off) (*(volatile u32_t *)(long) \
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(CONFIG_HPET_TIMER_BASE_ADDRESS + (off)))
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#define CLK_PERIOD_REG HPET_REG32(0x04) /* High dword of caps reg */
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#define GENERAL_CONF_REG HPET_REG32(0x10)
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#define MAIN_COUNTER_REG HPET_REG32(0xf0)
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#define TIMER0_CONF_REG HPET_REG32(0x100)
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#define TIMER0_COMPARATOR_REG HPET_REG32(0x108)
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/* GENERAL_CONF_REG bits */
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#define GCONF_ENABLE BIT(0)
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#define GCONF_LR BIT(1) /* legacy interrupt routing, disables PIT */
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/* TIMERn_CONF_REG bits */
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#define TCONF_INT_ENABLE BIT(2)
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#define TCONF_PERIODIC BIT(3)
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#define TCONF_VAL_SET BIT(6)
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#define TCONF_MODE32 BIT(8)
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#define MIN_DELAY 1000
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static struct k_spinlock lock;
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static unsigned int max_ticks;
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static unsigned int cyc_per_tick;
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static unsigned int last_count;
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static void hpet_isr(void *arg)
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{
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ARG_UNUSED(arg);
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k_spinlock_key_t key = k_spin_lock(&lock);
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u32_t now = MAIN_COUNTER_REG;
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u32_t dticks = (now - last_count) / cyc_per_tick;
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last_count += dticks * cyc_per_tick;
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL) ||
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IS_ENABLED(CONFIG_QEMU_TICKLESS_WORKAROUND)) {
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u32_t next = last_count + cyc_per_tick;
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if ((s32_t)(next - now) < MIN_DELAY) {
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next += cyc_per_tick;
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}
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TIMER0_COMPARATOR_REG = next;
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}
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k_spin_unlock(&lock, key);
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z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL) ? dticks : 1);
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}
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static void set_timer0_irq(unsigned int irq)
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{
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/* 5-bit IRQ field starting at bit 9 */
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u32_t val = (TIMER0_CONF_REG & ~(0x1f << 9)) | ((irq & 0x1f) << 9);
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TIMER0_CONF_REG = val;
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}
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int z_clock_driver_init(struct device *device)
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{
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extern int z_clock_hw_cycles_per_sec;
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u32_t hz;
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IRQ_CONNECT(CONFIG_HPET_TIMER_IRQ, CONFIG_HPET_TIMER_IRQ_PRIORITY,
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hpet_isr, 0, 0);
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set_timer0_irq(CONFIG_HPET_TIMER_IRQ);
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irq_enable(CONFIG_HPET_TIMER_IRQ);
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/* CLK_PERIOD_REG is in femtoseconds (1e-15 sec) */
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hz = (u32_t)(1000000000000000ull / CLK_PERIOD_REG);
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z_clock_hw_cycles_per_sec = hz;
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cyc_per_tick = hz / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
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/* Note: we set the legacy routing bit, because otherwise
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* nothing in Zephyr disables the PIT which then fires
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* interrupts into the same IRQ. But that means we're then
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* forced to use IRQ2 contra the way the kconfig IRQ selection
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* is supposed to work. Should fix this.
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*/
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GENERAL_CONF_REG |= GCONF_LR | GCONF_ENABLE;
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TIMER0_CONF_REG &= ~TCONF_PERIODIC;
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TIMER0_CONF_REG |= TCONF_MODE32;
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max_ticks = (0x7fffffff - cyc_per_tick) / cyc_per_tick;
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last_count = MAIN_COUNTER_REG;
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TIMER0_CONF_REG |= TCONF_INT_ENABLE;
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TIMER0_COMPARATOR_REG = MAIN_COUNTER_REG + cyc_per_tick;
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return 0;
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}
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void z_clock_set_timeout(s32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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#if defined(CONFIG_TICKLESS_KERNEL) && !defined(CONFIG_QEMU_TICKLESS_WORKAROUND)
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if (ticks == K_FOREVER && idle) {
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GENERAL_CONF_REG &= ~GCONF_ENABLE;
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return;
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}
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ticks = ticks == K_FOREVER ? max_ticks : ticks;
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ticks = MAX(MIN(ticks - 1, (s32_t)max_ticks), 0);
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k_spinlock_key_t key = k_spin_lock(&lock);
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u32_t now = MAIN_COUNTER_REG, cyc;
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/* Round up to next tick boundary */
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cyc = ticks * cyc_per_tick + (now - last_count) + (cyc_per_tick - 1);
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cyc = (cyc / cyc_per_tick) * cyc_per_tick;
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cyc += last_count;
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if ((cyc - now) < MIN_DELAY) {
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cyc += cyc_per_tick;
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}
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TIMER0_COMPARATOR_REG = cyc;
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k_spin_unlock(&lock, key);
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#endif
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}
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u32_t z_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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u32_t ret = (MAIN_COUNTER_REG - last_count) / cyc_per_tick;
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k_spin_unlock(&lock, key);
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return ret;
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}
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u32_t _timer_cycle_get_32(void)
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{
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return MAIN_COUNTER_REG;
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}
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void z_clock_idle_exit(void)
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{
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GENERAL_CONF_REG |= GCONF_ENABLE;
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}
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