There are some issues with the current version of the code, mainly the
improper use of the internal OSC8M as a source for the DFLL48m without
division. The DFLL48M is designed to accept a maximum of ~33KHz
at it's input, as higher values will bring the multiplier down,
leading to instability.
Also added the following features:
* Support for external HF oscillator (XOSC)
* Support for crystal/external oscillators on XOSC32K/XOSC
* Automatic dividers/multiplier computation based on DT cpu frequency
* Support for user configurable NVM wait states
* Added option to skip clock (re)initialization (bootloader usecase).
Tests were performed on a custom SAMD20G18 board using different clock
sources and cpu frequencies.
Clocks were routed to GPIO pins and observed on a scope.
According to the datasheet, architecture is identical on D21/R21.
Due to the nature of the internal architecture and the fact that
DFLL48M is not really meant to output anything other than 48MHZ
some combinations of requested DT cpu frequency and source
frequency will not result in a perfect match.
Mostly insipred by the SAML21 implementation.
Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
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