zephyr/arch/xtensa/core
Daniel Leung db495a5ebe xtensa: stop execution under simulator for double exception
If running under Xtensa simulator, it is good to tell simulator
to stop execution once we reach double exception, as the current
double exception handler is simply an endless loop. If we turn
on tracing in the simulator, the output file would contain
an infinite iteration of this endless loop, and the simulator
needs to be stopped manually before the file size goes out of
control. So we need to tell the simulator to stop once
we reach this point instead of doing an endless loop.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-01-23 10:09:18 +00:00
..
include arch: xtensa: core: include: Update header to use guard macros 2022-07-20 13:39:23 -05:00
offsets
startup
CMakeLists.txt arch/xtensa: Add CCOUNT-based timing API 2022-06-07 19:04:42 +02:00
coredump.c debug: coredump: add xtensa intel adsp, support toolchains 2022-06-23 15:44:45 -04:00
cpu_idle.c
crt1.S
debug_helpers_asm.S
fatal.c debug: coredump: add xtensa intel adsp, support toolchains 2022-06-23 15:44:45 -04:00
gdbstub.c
gen_zsr.py
irq_manage.c
irq_offload.c include: add missing zephyr/irq.h include 2022-10-17 22:57:39 +09:00
README-WINDOWS.rst
timing.c includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h> 2022-09-05 16:31:47 +02:00
tls.c
window_vectors.S
xcc_stubs.c
xtensa_backtrace.c xtensa: use lower-case hex in backtrace output 2022-09-09 14:09:33 -05:00
xtensa_intgen.py include: add zephyr/ on script generated #include 2022-05-27 15:20:27 -07:00
xtensa_intgen.tmpl
xtensa-asm2-util.S xtensa: stop execution under simulator for double exception 2023-01-23 10:09:18 +00:00
xtensa-asm2.c arch: xtensa: implement ARCH_EXCEPT 2022-06-23 15:44:45 -04:00