6c40abb99f
Introduce two configs to prepare to enable the safe exception stack for the kernel space. This is the preparation for enabling hardware stack guard. Also define the safe exception stack for kernel exception stack check. Signed-off-by: Jaxson Han <jaxson.han@arm.com>
307 lines
7.5 KiB
Plaintext
307 lines
7.5 KiB
Plaintext
# ARM64 core configuration options
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# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
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# SPDX-License-Identifier: Apache-2.0
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config CPU_CORTEX_A
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bool
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select CPU_CORTEX
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select HAS_FLASH_LOAD_OFFSET
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select SCHED_IPI_SUPPORTED if SMP
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select CPU_HAS_FPU
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select ARCH_HAS_SINGLE_THREAD_SUPPORT
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select CPU_HAS_DCACHE
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select CPU_HAS_ICACHE
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imply FPU
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imply FPU_SHARING
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help
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This option signifies the use of a CPU of the Cortex-A family.
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config CPU_AARCH64_CORTEX_R
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bool
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select CPU_CORTEX
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select HAS_FLASH_LOAD_OFFSET
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select CPU_HAS_DCACHE
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select CPU_HAS_ICACHE
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help
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This option signifies the use of a CPU of the Cortex-R 64-bit family.
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config CPU_CORTEX_A53
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bool
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select CPU_CORTEX_A
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select ARMV8_A
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help
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This option signifies the use of a Cortex-A53 CPU
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config CPU_CORTEX_A55
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bool
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select CPU_CORTEX_A
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select ARMV8_A
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help
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This option signifies the use of a Cortex-A55 CPU
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config CPU_CORTEX_A72
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bool
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select CPU_CORTEX_A
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select ARMV8_A
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help
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This option signifies the use of a Cortex-A72 CPU
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config CPU_CORTEX_R82
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bool
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select CPU_AARCH64_CORTEX_R
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select ARMV8_R
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help
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This option signifies the use of a Cortex-R82 CPU
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config HAS_ARM_SMCCC
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bool
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help
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Include support for the Secure Monitor Call (SMC) and Hypervisor
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Call (HVC) instructions on Armv7 and above architectures.
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config NUM_IRQS
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int
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config MAIN_STACK_SIZE
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default 4096
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config IDLE_STACK_SIZE
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default 4096
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config ISR_STACK_SIZE
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default 4096
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config TEST_EXTRA_STACK_SIZE
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default 2048
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config SYSTEM_WORKQUEUE_STACK_SIZE
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default 4096
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config CMSIS_THREAD_MAX_STACK_SIZE
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default 4096
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config CMSIS_V2_THREAD_MAX_STACK_SIZE
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default 4096
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config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
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default 4096
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config IPM_CONSOLE_STACK_SIZE
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default 2048
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config AARCH64_IMAGE_HEADER
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bool "Add image header"
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default y if ARM_MMU || ARM_MPU
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help
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This option enables standard ARM64 boot image header used by Linux
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and understood by loaders such as u-boot on Xen xl tool.
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config PRIVILEGED_STACK_SIZE
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default 4096
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config KOBJECT_TEXT_AREA
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default 512 if TEST
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config WAIT_AT_RESET_VECTOR
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bool "Wait at reset vector"
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default n
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help
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Spin at reset vector waiting for debugger to attach and resume
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execution
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config ARM64_SAFE_EXCEPTION_STACK
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bool "To enable the safe exception stack"
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help
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The safe exception stack is used for checking whether the kernel stack
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overflows during the exception happens from EL1. This stack is not
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used for user stack overflow checking, because kernel stack support
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the checking work.
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config ARM64_SAFE_EXCEPTION_STACK_SIZE
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int "The stack size of the safe exception stack"
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default 4096
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depends on ARM64_SAFE_EXCEPTION_STACK
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help
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The stack size of the safe exception stack. The safe exception stack
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requires to be enough to do the stack overflow check.
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if CPU_CORTEX_A
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config ARMV8_A_NS
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bool "ARMv8-A Normal World (Non-Secure world of Trustzone)"
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help
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This option signifies that Zephyr is entered in TrustZone
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Non-Secure state
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config ARMV8_A
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bool
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select ATOMIC_OPERATIONS_BUILTIN
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select CPU_HAS_MMU
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select ARCH_HAS_USERSPACE if ARM_MMU
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select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MMU
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help
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This option signifies the use of an ARMv8-A processor
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implementation.
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From https://developer.arm.com/products/architecture/cpu-architecture/a-profile:
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The Armv8-A architecture introduces the ability to use 64-bit and
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32-bit Execution states, known as AArch64 and AArch32 respectively.
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The AArch64 Execution state supports the A64 instruction set, holds
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addresses in 64-bit registers and allows instructions in the base
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instruction set to use 64-bit registers for their processing. The AArch32
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Execution state is a 32-bit Execution state that preserves backwards
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compatibility with the Armv7-A architecture and enhances that profile
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so that it can support some features included in the AArch64 state.
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It supports the T32 and A32 instruction sets.
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endif # CPU_CORTEX_A
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if CPU_AARCH64_CORTEX_R
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config ARMV8_R
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bool
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select ATOMIC_OPERATIONS_BUILTIN
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select SCHED_IPI_SUPPORTED if SMP
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select ARCH_HAS_USERSPACE if ARM_MPU
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help
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This option signifies the use of an ARMv8-R processor
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implementation.
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From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
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The Armv8-R architecture targets at the Real-time profile. It introduces
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virtualization at the highest security level while retaining the
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Protected Memory System Architecture (PMSA) based on a Memory Protection
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Unit (MPU). It supports the A32 and T32 instruction sets.
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rsource "cortex_r/Kconfig"
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endif # CPU_AARCH64_CORTEX_R
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if CPU_CORTEX_A || CPU_AARCH64_CORTEX_R
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config GEN_ISR_TABLES
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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config ARM_MMU
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bool "ARM MMU Support"
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default n if CPU_AARCH64_CORTEX_R
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default y
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select MMU
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select SRAM_REGION_PERMISSIONS
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select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
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select ARCH_MEM_DOMAIN_DATA if USERSPACE
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help
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Memory Management Unit support.
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config EXCEPTION_DEBUG
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bool "Unhandled exception debugging information"
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default y
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depends on LOG
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help
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Print human-readable information about exception vectors, cause codes,
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and parameters, at a cost of code/data size for the human-readable
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strings.
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config XIP
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select AARCH64_IMAGE_HEADER
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config ARM64_SET_VMPIDR_EL2
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bool "Set VMPIDR_EL2 at EL2 stage"
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help
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VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
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This is the value returned by EL1 reads of MPIDR_EL1.
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This register may already be set by bootloader at the EL2 stage, if
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not, Zephyr should set it.
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if ARM_MMU
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config MMU_PAGE_SIZE
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default 0x1000
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choice
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prompt "Virtual address space size"
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default ARM64_VA_BITS_32
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help
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Allows choosing one of multiple possible virtual address
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space sizes. The level of translation table is determined by
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a combination of page size and virtual address space size.
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config ARM64_VA_BITS_32
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bool "32-bit"
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config ARM64_VA_BITS_36
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bool "36-bit"
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config ARM64_VA_BITS_40
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bool "40-bit"
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config ARM64_VA_BITS_42
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bool "42-bit"
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config ARM64_VA_BITS_48
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bool "48-bit"
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endchoice
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config ARM64_VA_BITS
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int
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default 32 if ARM64_VA_BITS_32
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default 36 if ARM64_VA_BITS_36
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default 40 if ARM64_VA_BITS_40
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default 42 if ARM64_VA_BITS_42
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default 48 if ARM64_VA_BITS_48
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choice
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prompt "Physical address space size"
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default ARM64_PA_BITS_32
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help
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Choose the maximum physical address range that the kernel will
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support.
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config ARM64_PA_BITS_32
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bool "32-bit"
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config ARM64_PA_BITS_36
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bool "36-bit"
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config ARM64_PA_BITS_40
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bool "40-bit"
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config ARM64_PA_BITS_42
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bool "42-bit"
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config ARM64_PA_BITS_48
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bool "48-bit"
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endchoice
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config ARM64_PA_BITS
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int
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default 32 if ARM64_PA_BITS_32
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default 36 if ARM64_PA_BITS_36
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default 40 if ARM64_PA_BITS_40
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default 42 if ARM64_PA_BITS_42
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default 48 if ARM64_PA_BITS_48
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config MAX_XLAT_TABLES
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int "Maximum numbers of translation tables"
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default 20 if USERSPACE && (ARM64_VA_BITS >= 40)
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default 16 if USERSPACE
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default 12 if (ARM64_VA_BITS >= 40)
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default 8
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help
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This option specifies the maximum numbers of translation tables.
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Based on this, translation tables are allocated at compile time and
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used at runtime as needed. If the runtime need exceeds preallocated
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numbers of translation tables, it will result in assert. Number of
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translation tables required is decided based on how many discrete
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memory regions (both normal and device memory) are present on given
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platform and how much granularity is required while assigning
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attributes to these memory regions.
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endif # ARM_MMU
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endif # CPU_CORTEX_A || CPU_AARCH64_CORTEX_R
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