5b9378ab7e
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly. Linker scripts had some alarming comments about data/BSS overlap, but the beginning of BSS is aligned so this can't happen even if the end of data isn't. The common code doesn't use fake pointer values for the number of words in these sections, don't compute or export them. Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
131 lines
3.0 KiB
C
131 lines
3.0 KiB
C
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Full C support initialization
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*
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*
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* Initialization of full C support: zero the .bss, copy the .data if XIP,
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* call _Cstart().
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*
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* Stack is available in this module, but not the global data/bss until their
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* initialization is performed.
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*/
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#include <stdint.h>
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#include <toolchain.h>
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#include <linker-defs.h>
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#include <arch/arc/v2/aux_regs.h>
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#include <nano_internal.h>
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/**
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*
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* @brief Disable the i-cache if present
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*
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* For those ARC CPUs that have a i-cache present,
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* invalidate the i-cache and then disable it.
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*
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* @return N/A
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*/
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static void disable_icache(void)
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{
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unsigned int val;
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val = _arc_v2_aux_reg_read(_ARC_V2_I_CACHE_BUILD);
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val &= 0xff; /* version field */
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if (val == 0) {
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return; /* skip if i-cache is not present */
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}
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_arc_v2_aux_reg_write(_ARC_V2_IC_IVIC, 0);
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__asm__ __volatile__ ("nop");
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_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, 1);
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}
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/**
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*
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* @brief Invalidate the data cache if present
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*
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* For those ARC CPUs that have a data cache present,
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* invalidate the data cache.
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*
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* @return N/A
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*/
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static void invalidate_dcache(void)
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{
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unsigned int val;
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val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
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val &= 0xff; /* version field */
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if (val == 0) {
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return; /* skip if d-cache is not present */
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}
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_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
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}
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/**
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*
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* @brief Adjust the vector table base
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*
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* Set the vector table base if the value found in the
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* _ARC_V2_IRQ_VECT_BASE auxiliary register is different from the
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* _VectorTable known by software. It is important to do this very early
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* so that exception vectors can be handled.
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*
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* @return N/A
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*/
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static void adjust_vector_table_base(void)
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{
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extern struct vector_table _VectorTable;
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unsigned int vbr;
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/* if the compiled-in vector table is different
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* from the base address known by the ARC CPU,
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* set the vector base to the compiled-in address.
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*/
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vbr = _arc_v2_aux_reg_read(_ARC_V2_IRQ_VECT_BASE);
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vbr &= 0xfffffc00;
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if (vbr != (unsigned int)&_VectorTable) {
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_arc_v2_aux_reg_write(_ARC_V2_IRQ_VECT_BASE,
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(unsigned int)&_VectorTable);
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}
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}
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extern FUNC_NORETURN void _Cstart(void);
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/**
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*
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* @brief Prepare to and run C code
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*
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* This routine prepares for the execution of and runs C code.
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*
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* @return N/A
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*/
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void _PrepC(void)
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{
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disable_icache();
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invalidate_dcache();
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adjust_vector_table_base();
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_bss_zero();
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_data_copy();
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_Cstart();
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CODE_UNREACHABLE;
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}
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