c8a9634a30
Currently the lazy fpu saving algorithm in arm64 is using the fpu_owner pointer from the cpu structure to understand the owner of the context in the cpu and save it in case someone different from the owner is accessing the fpu. The semantics for memory consistency across smp systems is quite prone to errors and reworks on the current code might miss some barriers that could lead to inconsistent state across cores, so to overcome the issue, use atomics to hide the complexity and be sure that the code will behave as intended. While there, add some isb barriers after writes to cpacr_el1, following the guidance of ARM ARM specs about writes on system registers. Signed-off-by: Luca Fancellu <luca.fancellu@arm.com> |
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| core | ||
| include | ||
| CMakeLists.txt | ||
| Kconfig | ||