Karsten Koenig 2e61137cc9 arch: riscv: thread: Init soc context on stack ... The optional SOC_CONTEXT carries processor state registers that need to be initialized properly to avoid uninitialized memory read as processor state. In particular on the RV32M1 the extra soc context stores a state for special loop instructions, and loading non zero values will have the core assume it is in a loop. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>		2020-07-13 15:00:19 -05:00
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arc	boards: arc: emsdp: fix secure config for emsdp_em7d_esp	2020-06-09 11:30:37 +02:00
arm	soc: arm: viper: Fix callee saved register corruption in el3 init	2020-07-13 11:53:36 +02:00
nios2	soc: nios2: Cleanup linker scripts to use new DTS macros	2020-04-30 20:59:13 -05:00
posix	zephyr: replace zephyr integer types with C99 types	2020-06-08 08:23:57 -05:00
riscv	arch: riscv: thread: Init soc context on stack	2020-07-13 15:00:19 -05:00
x86	arch/x86: early_serial cleanup	2020-07-08 12:34:09 +02:00
xtensa	config: Rename TEXT_SECTION_OFFSET to ROM_START_OFFSET	2020-07-09 14:02:38 -04:00
Kconfig	linker: Remove deprecated Kconfig options related to linker scripts	2020-06-12 11:14:28 +02:00