dbada63eee
Some checkpatch issues were solved by scripts leaving other problems such as alignment and indentation issues. In order to comply with the defined coding style the following fixes were made: - Fixed the function declaration moving the parameters' comments above the function in accordance to the doxygen format. - Fixed functions' opening and closing brackets. These brackets should not be indented. - Fixed the 'if', 'for' and 'while' statements adding the brackets around the sentence. - Fixed comments' alignment. - Fixed indentation. The work was done manually and submitted as one commit. I didn't separate these changes in different commits because they were fixed all at once. Basically, all errors were fixed in every file at once. Change-Id: Icc94a10bfd2cff82007ce60df23b2ccd4c30268d Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
164 lines
4.5 KiB
C
164 lines
4.5 KiB
C
/* irq-test-common.h - IRQ utilities for tests */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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Interrupt stuff, abstracted across CPU architectures.
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*/
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#ifndef _IRQ_TEST_COMMON__H_
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#define _IRQ_TEST_COMMON__H_
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/* defines */
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#if defined(VXMICRO_ARCH_x86)
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#define IRQ_PRIORITY 3
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#elif defined(VXMICRO_ARCH_arm)
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#if defined(CONFIG_CPU_CORTEXM)
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#define IRQ_PRIORITY _EXC_PRIO(3)
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#endif /* CONFIG_CPU_CORTEXM */
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#endif
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/*
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* NUM_SW_IRQS must be defined before this file is included, and it
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* currently only supports 1 or 2 as valid values.
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*/
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#if !defined(NUM_SW_IRQS)
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#error NUM_SW_IRQS must be defined before including irq-test-common.h
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#elif NUM_SW_IRQS < 1 || NUM_SW_IRQS > 2
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#error NUM_SW_IRQS only supports 1 or 2 IRQs
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#endif
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#if defined(VXMICRO_ARCH_x86)
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static NANO_CPU_INT_STUB_DECL(nanoIntStub1);
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#if NUM_SW_IRQS >= 2
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static NANO_CPU_INT_STUB_DECL(nanoIntStub2);
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#endif /* NUM_SW_IRQS >= 2 */
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#endif
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typedef void (*vvfn)(void); /* void-void function pointer */
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typedef void (*vvpfn)(void *); /* void-void_pointer function pointer */
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#if defined(VXMICRO_ARCH_x86)
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/*
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* Opcode for generating a software interrupt. The ISR associated with each
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* of these software interrupts will call either nano_isr_lifo_put() or
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* nano_isr_lifo_get(). The imm8 data in the opcode sequence will need to be
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* filled in after calling irq_connect().
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*/
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static char sw_isr_trigger_0[] = {
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0xcd, /* OPCODE: INT imm8 */
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0x00, /* imm8 data (vector to trigger) filled in at runtime */
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0xc3 /* OPCODE: RET (near) */
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};
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#if NUM_SW_IRQS >= 2
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static char sw_isr_trigger_1[] = {
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/* same as above */
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0xcd,
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0x00,
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0xc3
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};
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#endif /* NUM_SW_IRQS >= 2 */
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#elif defined(VXMICRO_ARCH_arm)
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#if defined(CONFIG_CPU_CORTEXM)
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#include <nanokernel.h>
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static inline void sw_isr_trigger_0(void)
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{
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_NvicSwInterruptTrigger(0);
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}
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#if NUM_SW_IRQS >= 2
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static inline void sw_isr_trigger_1(void)
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{
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_NvicSwInterruptTrigger(1);
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}
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* CONFIG_CPU_CORTEXM */
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#endif
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struct isrInitInfo {
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vvpfn isr[2];
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void *arg[2];
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};
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/*******************************************************************************
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*
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* initIRQ - init interrupts
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*
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*/
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static int initIRQ(struct isrInitInfo *i)
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{
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#if defined(VXMICRO_ARCH_x86)
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int vector; /* vector to which interrupt is connected */
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if (i->isr[0]) {
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vector = irq_connect(NANO_SOFT_IRQ, IRQ_PRIORITY, i->isr[0],
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i->arg[0], nanoIntStub1);
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if (-1 == vector) {
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return -1;
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}
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sw_isr_trigger_0[1] = vector;
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}
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#if NUM_SW_IRQS >= 2
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if (i->isr[1]) {
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vector = irq_connect(NANO_SOFT_IRQ, IRQ_PRIORITY, i->isr[1],
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i->arg[1], nanoIntStub2);
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if (-1 == vector) {
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return -1;
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}
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sw_isr_trigger_1[1] = vector;
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}
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#endif /* NUM_SW_IRQS >= 2 */
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#elif defined(VXMICRO_ARCH_arm)
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#if defined(CONFIG_CPU_CORTEXM)
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if (i->isr[0]) {
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(void) irq_connect(0, IRQ_PRIORITY, i->isr[0], i->arg[0]);
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irq_enable(0);
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}
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if (i->isr[1]) {
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(void) irq_connect(1, IRQ_PRIORITY, i->isr[1], i->arg[1]);
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irq_enable(1);
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}
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#endif /* CONFIG_CPU_CORTEXM */
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#endif /* VXMICRO_ARCH_x86 */
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return 0;
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}
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#endif /* _IRQ_TEST_COMMON__H_ */
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