500 lines
15 KiB
ArmAsm
500 lines
15 KiB
ArmAsm
/* nanoatomic.s - VxMicro nanokernel atomic operators for IA-32 */
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/*
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* Copyright (c) 2011-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This module provides the atomic operators for IA-32 architectures on BSPs
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that support the LOCK prefix instruction.
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The atomic operations are guaranteed to be atomic with respect to interrupt
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service routines, and to operations performed by peer processors.
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INTERNAL
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These operators are currently unavailable to user space applications,
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as there is no requirement for this capability.
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*/
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/* includes */
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#if !defined(CONFIG_LOCK_INSTRUCTION_UNSUPPORTED)
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#define _ASMLANGUAGE
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#include <nanokernel/x86/asm.h>
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/* exports (public APIs) */
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GTEXT(atomic_cas)
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GTEXT(atomic_add)
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GTEXT(atomic_sub)
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GTEXT(atomic_inc)
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GTEXT(atomic_dec)
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GTEXT(atomic_get)
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GTEXT(atomic_set)
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GTEXT(atomic_clear)
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GTEXT(atomic_or)
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GTEXT(atomic_xor)
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GTEXT(atomic_and)
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GTEXT(atomic_nand)
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/*******************************************************************************
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*
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* atomic_cas - atomic compare-and-set primitive
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*
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* This routine provides the compare-and-set operator. If the original value at
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* <target> equals <oldValue>, then <newValue> is stored at <target> and the
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* function returns 1.
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*
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* If the original value at <target> does not equal <oldValue>, then the store
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* is not done and the function returns 0.
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*
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* The reading of the original value at <target>, the comparison,
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* and the write of the new value (if it occurs) all happen atomically with
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* respect to both interrupts and accesses of other processors to <target>.
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*
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* RETURNS: Returns 1 if <newValue> is written, 0 otherwise.
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*
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* int atomic_cas
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* (
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* atomic_t * target, /@ address to be tested @/
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* atomic_val_t oldValue, /@ value to compare against @/
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* atomic_val_t newValue /@ value to compare against @/
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* )
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*
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* INTERNAL
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* The 'cmpxchg' instruction is NOT supported on processor prior to the 80486
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*/
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SECTION_FUNC(TEXT, atomic_cas)
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movl SP_ARG1(%esp),%edx /* get address */
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movl SP_ARG2(%esp),%eax /* get oldValue to cmp */
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movl SP_ARG3(%esp),%ecx /* get newValue to set */
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lock /* lock the bus during the next inst */
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cmpxchg %ecx,(%edx) /* if (%eax == (%edx) */
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/* {ZF = 1; (%edx) = %ecx;} */
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/* else */
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/* {ZF = 0; %eax = (%edx);} */
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jne atomic_cas1
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movl $1,%eax /* set return status to 1 */
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ret
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BRANCH_LABEL(atomic_cas1)
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xorl %eax,%eax /* set return status to 0 */
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ret
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/*******************************************************************************
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*
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* atomic_add - atomic add primitive
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*
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* This routine provides the atomic addition operator. The <value> is
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* atomically added to the value at <target>, placing the result at <target>,
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* and the old value from <target> is returned.
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*
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* RETURNS: The previous value from <target>
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*
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* atomic_val_t atomic_add
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* (
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* atomic_t * target, /@ memory location to add to @/
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* atomic_val_t value /@ value to add @/
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* )
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*
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* INTERNAL
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* The 'xadd' instruction is NOT supported on processor prior to the 80486
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*/
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SECTION_FUNC(TEXT, atomic_add)
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movl SP_ARG1(%esp),%edx /* get address */
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movl SP_ARG2(%esp),%eax /* get value to add */
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lock /* lock the bus during the next inst */
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xadd %eax,(%edx) /* TMP = %eax + (%edx) */
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/* %eax = (%edx) */
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/* (%edx) = TMP */
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ret
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/*******************************************************************************
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*
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* atomic_sub - atomic subtraction primitive
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*
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* This routine provides the atomic subtraction operator. The <value> is
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* atomically subtracted from the value at <target>, placing the result at
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* <target>, and the old value from <target> is returned.
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*
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* RETURNS: The previous value from <target>
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*
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* atomic_val_t atomic_sub
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* (
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* atomic_t * target, /@ memory location to subtract from @/
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* atomic_val_t value /@ value to subtract @/
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* )
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*
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* INTERNAL
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* The 'xadd' instruction is NOT supported on processor prior to the 80486
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*/
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SECTION_FUNC(TEXT, atomic_sub)
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movl SP_ARG1(%esp),%edx /* get address */
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movl SP_ARG2(%esp),%eax /* get value to add */
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negl %eax /* Negate %eax... */
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lock /* lock the bus during the next inst */
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xadd %eax,(%edx) /* TMP = %eax + (%edx) */
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/* %eax = (%edx) */
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/* (%edx) = TMP */
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ret
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/*******************************************************************************
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*
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* atomic_inc - atomic increment primitive
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*
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* This routine provides the atomic increment operator. The value at <target>
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* is atomically incremented by 1, and the old value from <target> is returned.
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*
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* RETURNS: The value from <target> before the increment
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*
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* atomic_val_t atomic_inc
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* (
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* atomic_t *target /@ memory location to increment @/
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* )
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*
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* INTERNAL
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* The 'xadd' instruction is NOT supported on processor prior to the 80486
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*/
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SECTION_FUNC(TEXT, atomic_inc)
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movl SP_ARG1(%esp),%edx /* get address */
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xorl %eax, %eax
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incl %eax /* increment by 1 */
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lock /* lock the bus during the next inst */
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xadd %eax,(%edx) /* TMP = %eax + (%edx) */
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/* %eax = (%edx) */
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/* (%edx) = TMP */
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ret
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/*******************************************************************************
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*
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* atomic_dec - atomic decrement primitive
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*
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* This routine provides the atomic decrement operator. The value at <target>
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* is atomically decremented by 1, and the old value from <target> is returned.
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*
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* RETURNS: The value from <target> prior to the decrement
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*
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* atomic_val_t atomic_dec
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* (
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* atomic_t *target /@ memory location to decrement @/
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* )
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*
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* INTERNAL
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* The 'xadd' instruction is NOT supported on processor prior to the 80486
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*/
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SECTION_FUNC(TEXT, atomic_dec)
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movl SP_ARG1(%esp),%edx /* get address */
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orl $-1,%eax /* dec by 1 */
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lock /* lock the bus during the next inst */
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xadd %eax,(%edx) /* TMP = %eax + (%edx) */
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/* %eax = (%edx) */
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/* (%edx) = TMP */
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ret
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/*******************************************************************************
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*
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* atomic_get - atomic get primitive
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*
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* This routine provides the atomic get primitive to atomically read
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* a value from <target>. It simply does an ordinary load. Note that <target>
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* is expected to be aligned to a 4-byte boundary.
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*
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* RETURNS: The value read from <target>
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*
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* atomic_t atomic_get
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* (
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* atomic_t *target /@ memory location to read from @/
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* )
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*
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*/
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SECTION_FUNC(TEXT, atomic_get)
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movl SP_ARG1(%esp),%edx /* get address */
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movl (%edx), %eax /* get value */
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ret
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/*******************************************************************************
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*
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* atomic_set - atomic get-and-set primitive
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*
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* This routine provides the atomic set operator. The <value> is atomically
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* written at <target> and the previous value at <target> is returned.
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*
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* RETURNS: The previous value from <target>
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*
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* atomic_val_t atomic_set
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* (
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* atomic_t *target, /@ memory location to write to @/
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* atomic_val_t value /@ value to set @/
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* )
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*
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* INTERNAL
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* The XCHG instruction is executed on the specified address to
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* swap in value. The value swapped out is returned by this function.
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*/
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SECTION_FUNC(TEXT, atomic_set)
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movl SP_ARG1(%esp),%edx /* get address */
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movl SP_ARG2(%esp),%eax /* get value to set */
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/*
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* The 'lock' prefix is not required with the 'xchg' instruction.
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* According to the IA-32 instruction reference manual:
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*
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* "If a memory operand is referenced, the processor's locking
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* protocol is automatically implemented for the duration of
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* the exchange operation, regardless of the presence
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* or absence of the LOCK prefix or of the value of the IOPL."
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*/
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xchg %eax,(%edx) /* set value with bus-lock */
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ret
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/*******************************************************************************
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*
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* atomic_clear - atomic clear primitive
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*
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* This routine provides the atomic clear operator. The value of 0 is atomically
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* written at <target> and the previous value at <target> is returned. (Hence,
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* atomic_clear(pAtomicVar) is equivalent to atomic_set(pAtomicVar, 0).)
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*
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* RETURNS: The previous value from <target>
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*
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* atomic_val_t atomic_clear
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* (
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* atomic_t *target /@ memory location to write to @/
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* )
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*
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*/
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SECTION_FUNC(TEXT, atomic_clear)
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movl SP_ARG1(%esp),%edx /* get address */
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xorl %eax,%eax /* clear value to set */
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/*
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* The 'lock' prefix is not required with the 'xchg' instruction.
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* According to the IA-32 instruction reference manual:
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*
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* "If a memory operand is referenced, the processor's locking
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* protocol is automatically implemented for the duration of
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* the exchange operation, regardless of the presence
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* or absence of the LOCK prefix or of the value of the IOPL."
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*/
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xchg %eax,(%edx) /* swap 'clear' value with bus-lock */
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ret
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/*******************************************************************************
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*
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* atomic_or - atomic bitwise inclusive OR primitive
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*
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* This routine provides the atomic bitwise inclusive OR operator. The <value>
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* is atomically bitwise OR'ed with the value at <target>, placing the result
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* at <target>, and the previous value at <target> is returned.
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*
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* RETURNS: The previous value from <target>
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*
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* atomic_val_t atomic_or
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* (
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* atomic_t *target, /@ memory location to be modified @/
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* atomic_val_t value /@ value to OR @/
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* )
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*
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* INTERNAL
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* The 'cmpxchg' instruction is NOT supported on processor prior to the 80486
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*/
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SECTION_FUNC(TEXT, atomic_or)
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movl SP_ARG1(%esp),%edx /* get address */
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movl (%edx),%eax /* get old value */
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BRANCH_LABEL(atomic_or_retry)
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movl SP_ARG2(%esp),%ecx /* get value to OR */
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orl %eax, %ecx
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lock /* lock the bus during the next inst */
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cmpxchg %ecx,(%edx) /* if (%eax == (%edx)) */
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/* {ZF = 1 ; (%edx) = %ecx;} */
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/* else */
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/* {ZF = 0 ; %eax = (%edx);} */
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jnz atomic_or_retry
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ret
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/*******************************************************************************
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*
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* atomic_xor - atomic bitwise exclusive OR (XOR) primitive
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*
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* This routine provides the atomic bitwise exclusive OR operator. The <value>
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* is atomically bitwise XOR'ed with the value at <target>, placing the result
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* at <target>, and the previous value at <target> is returned.
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*
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* RETURNS: The previous value from <target>
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*
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* atomic_val_t atomic_xor
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* (
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* atomic_t *target, /@ memory location to be modified @/
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* atomic_t value /@ value to XOR @/
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* )
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*
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* INTERNAL
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* The 'cmpxchg' instruction is NOT supported on processor prior to the 80486
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*/
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SECTION_FUNC(TEXT, atomic_xor)
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movl SP_ARG1(%esp),%edx /* get address */
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movl (%edx),%eax /* get old value */
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BRANCH_LABEL(atomic_xor_retry)
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movl SP_ARG2(%esp),%ecx /* get value to set */
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xorl %eax, %ecx
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lock /* lock the bus during the next inst */
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cmpxchg %ecx,(%edx) /* if (%eax == (%edx)) */
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/* {ZF = 1 ; (%edx) = %ecx;} */
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/* else */
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/* {ZF = 0 ; %eax = (%edx);} */
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jnz atomic_xor_retry
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ret
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/*******************************************************************************
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*
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* atomic_and - atomic bitwise AND primitive
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*
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* This routine provides the atomic bitwise AND operator. The <value> is
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* atomically bitwise AND'ed with the value at <target>, placing the result
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* at <target>, and the previous value at <target> is returned.
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*
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* RETURNS: The previous value from <target>
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*
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* atomic_val_t atomic_and
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* (
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* atomic_t *target, /@ memory location to be modified @/
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* atomic_val_t value /@ value to AND @/
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* )
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*
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* INTERNAL
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* The 'cmpxchg' instruction is NOT supported on processor prior to the 80486
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*/
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SECTION_FUNC(TEXT, atomic_and)
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movl SP_ARG1(%esp),%edx /* get address */
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movl (%edx),%eax /* get old value */
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BRANCH_LABEL(atomic_and_retry)
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movl SP_ARG2(%esp),%ecx /* get value to set */
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andl %eax, %ecx
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lock /* lock the bus during the next inst */
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cmpxchg %ecx,(%edx) /* if (%eax == (%edx)) */
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/* {ZF = 1 ; (%edx) = %ecx;} */
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/* else */
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/* {ZF = 0 ; %eax = (%edx);} */
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jnz atomic_and_retry
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ret
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/*******************************************************************************
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*
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* atomic_nand - atomic bitwise NAND primitive
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*
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* This routine provides the atomic bitwise NAND operator. The <value> is
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* atomically bitwise NAND'ed with the value at <target>, placing the result
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* at <target>, and the previous value at <target> is returned.
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*
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* RETURNS: The previous value from <target>
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*
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* atomic_val_t atomic_nand
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* (
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* atomic_t * target, /@ memory location to be modified @/
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* atomic_val_t value /@ value to NAND @/
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* )
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*
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* INTERNAL
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* The 'cmpxchg' instruction is NOT supported on processor prior to the 80486
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*/
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SECTION_FUNC(TEXT, atomic_nand)
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movl SP_ARG1(%esp),%edx /* get address */
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movl (%edx),%eax /* get old value */
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BRANCH_LABEL(atomic_nand_retry)
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movl SP_ARG2(%esp),%ecx /* get value to nand with old value */
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andl %eax,%ecx
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not %ecx
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lock /* lock the bus during the next inst */
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cmpxchg %ecx,(%edx) /* if (%eax == (%edx)) */
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/* {ZF = 1 ; (%edx) = %ecx;} */
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/* else */
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/* {ZF = 0 ; %eax = (%edx);} */
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jnz atomic_nand_retry
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ret
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#endif /* !CONFIG_LOCK_INSTRUCTION_UNSUPPORTED */
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