db3cd1a833
On Cortex-M33 the access to peripheral registers doesn't act as a data synchronization barrier for memory accesses to normal memory. So before triggering any TASKS for cache operations we need to make sure the core doesn't have any pending memory transactions. Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no> |
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| .. | ||
| cache_andes_l2.h | ||
| cache_andes.c | ||
| cache_aspeed.c | ||
| cache_handlers.c | ||
| cache_nrf.c | ||
| cache_nxp_xcache.c | ||
| cache_stm32.c | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.andes | ||
| Kconfig.aspeed | ||
| Kconfig.nrf | ||
| Kconfig.nxp_xcache | ||
| Kconfig.stm32 | ||