f5794923a1
AST10x0 series SOCs provide the reset controller through the syscon hardware block. The current driver supports the reset line assert, deassert and status for the hardware IPs embedded in the SOC. Each reset line has an ID that can simply map to a bit in syscon registers RESET_CTRL0_ASSERT (group 0) or RESET_CTRL1_ASSERT (group 1). Write bits to RESET_CTRL0_DEASSERT or RESET_CTRL1_DEASSERT will clean the corresponding bits in RESET_CTRL0_ASSERT or RESET_CTRL1_ASSERT registers. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> |
||
|---|---|---|
| .. | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.aspeed | ||
| Kconfig.gd32 | ||
| Kconfig.rpi_pico | ||
| reset_ast10x0.c | ||
| reset_gd32.c | ||
| reset_rpi_pico.c | ||