8ac6f74a7d
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds support for the "sample_controller" SoC (used by qemu_xtensa) as demonstration. As Xtensa lacks a common linker script at the arch level, enabling it for each platform will be a piecemeal effort. This patch adds it to the `soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is set to be called "RAM", and hooks are inserted so that gen_relocate_app.py can add the relevant linker bits. Also, `tests/application_developent/code_relocation` was tweaked to support the qemu_xtensa platform. Basically, add the relevant linker script and ensure that relevant memory regions have their program header (PHDR) associated. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
33 lines
915 B
CMake
33 lines
915 B
CMake
# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(code_relocation)
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FILE(GLOB app_sources src/*.c)
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target_sources(app PRIVATE ${app_sources})
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if (CONFIG_BOARD_QEMU_XTENSA)
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set(RAM_PHDR :sram0_phdr)
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set(SRAM2_PHDR :sram2_phdr)
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endif()
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# Code relocation feature
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zephyr_code_relocate(src/test_file1.c "SRAM2 ${SRAM2_PHDR}")
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zephyr_code_relocate(src/test_file2.c "RAM ${RAM_PHDR}")
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zephyr_code_relocate(src/test_file3.c SRAM2_LITERAL)
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zephyr_code_relocate(src/test_file3.c SRAM2_TEXT)
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zephyr_code_relocate(src/test_file3.c RAM_DATA)
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zephyr_code_relocate(src/test_file3.c SRAM2_BSS)
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zephyr_code_relocate(../../../kernel/sem.c "RAM ${RAM_PHDR}")
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if (CONFIG_RELOCATE_TO_ITCM)
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zephyr_code_relocate(../../../lib/libc/minimal/source/string/string.c ITCM_TEXT)
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endif()
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zephyr_linker_sources(SECTIONS custom-sections.ld)
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