3580a6bcec
Based on the STM32F10x driver. Removing old code as we need to use the bus number when dealing with 4 possible peripherals. Change-Id: Id0263aa008e9b039ff9a00339e5622e289ffdf99 Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
126 lines
3.9 KiB
C
126 lines
3.9 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* (c) 2016 Linaro Limited.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _STM32F4_CLOCK_CONTROL_H_
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#define _STM32F4_CLOCK_CONTROL_H_
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/**
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* @file
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*
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* @brief Clock subsystem IDs for STM32F4 family
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*/
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/* Bus */
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enum {
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STM32F4X_CLOCK_BUS_AHB1,
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STM32F4X_CLOCK_BUS_AHB2,
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STM32F4X_CLOCK_BUS_APB1,
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STM32F4X_CLOCK_BUS_APB2,
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};
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/* AHB1 pins */
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enum {
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/* AHB1 */
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STM32F4X_CLOCK_ENABLE_GPIOA = 1 << 0,
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STM32F4X_CLOCK_ENABLE_GPIOB = 1 << 1,
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STM32F4X_CLOCK_ENABLE_GPIOC = 1 << 2,
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STM32F4X_CLOCK_ENABLE_GPIOD = 1 << 3,
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STM32F4X_CLOCK_ENABLE_GPIOE = 1 << 4,
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STM32F4X_CLOCK_ENABLE_GPIOF = 1 << 5,
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STM32F4X_CLOCK_ENABLE_GPIOG = 1 << 6,
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STM32F4X_CLOCK_ENABLE_GPIOH = 1 << 7,
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STM32F4X_CLOCK_ENABLE_GPIOI = 1 << 8,
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STM32F4X_CLOCK_ENABLE_GPIOJ = 1 << 9,
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STM32F4X_CLOCK_ENABLE_GPIOK = 1 << 10,
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STM32F4X_CLOCK_ENABLE_CRC = 1 << 12,
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STM32F4X_CLOCK_ENABLE_BKPSRAM = 1 << 14,
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STM32F4X_CLOCK_ENABLE_CCMDATARAM = 1 << 16,
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STM32F4X_CLOCK_ENABLE_DMA1 = 1 << 21,
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STM32F4X_CLOCK_ENABLE_DMA2 = 1 << 22,
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STM32F4X_CLOCK_ENABLE_ETHMAC = 1 << 25,
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STM32F4X_CLOCK_ENABLE_ETHMACTX = 1 << 26,
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STM32F4X_CLOCK_ENABLE_ETHMACRX = 1 << 27,
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STM32F4X_CLOCK_ENABLE_ETHMACPTP = 1 << 28,
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STM32F4X_CLOCK_ENABLE_OTGHS = 1 << 29,
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STM32F4X_CLOCK_ENABLE_OTGHSULPI = 1 << 30,
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};
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/* AHB2 pins */
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enum {
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STM32F4X_CLOCK_ENABLE_DCMI = 1 << 0,
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STM32F4X_CLOCK_ENABLE_CRYP = 1 << 4,
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STM32F4X_CLOCK_ENABLE_HASH = 1 << 5,
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STM32F4X_CLOCK_ENABLE_RNG = 1 << 6,
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STM32F4X_CLOCK_ENABLE_OTGFS = 1 << 7,
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};
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/* APB1 pins */
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enum {
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STM32F4X_CLOCK_ENABLE_TIM2 = 1 << 0,
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STM32F4X_CLOCK_ENABLE_TIM3 = 1 << 1,
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STM32F4X_CLOCK_ENABLE_TIM4 = 1 << 2,
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STM32F4X_CLOCK_ENABLE_TIM5 = 1 << 3,
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STM32F4X_CLOCK_ENABLE_TIM6 = 1 << 4,
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STM32F4X_CLOCK_ENABLE_TIM7 = 1 << 5,
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STM32F4X_CLOCK_ENABLE_TIM12 = 1 << 6,
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STM32F4X_CLOCK_ENABLE_TIM13 = 1 << 7,
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STM32F4X_CLOCK_ENABLE_TIM14 = 1 << 8,
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STM32F4X_CLOCK_ENABLE_WWDG = 1 << 11,
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STM32F4X_CLOCK_ENABLE_SPI2 = 1 << 14,
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STM32F4X_CLOCK_ENABLE_SPI3 = 1 << 15,
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STM32F4X_CLOCK_ENABLE_USART2 = 1 << 17,
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STM32F4X_CLOCK_ENABLE_USART3 = 1 << 18,
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STM32F4X_CLOCK_ENABLE_UART4 = 1 << 19,
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STM32F4X_CLOCK_ENABLE_UART5 = 1 << 20,
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STM32F4X_CLOCK_ENABLE_I2C1 = 1 << 21,
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STM32F4X_CLOCK_ENABLE_I2C2 = 1 << 22,
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STM32F4X_CLOCK_ENABLE_I2C3 = 1 << 23,
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STM32F4X_CLOCK_ENABLE_CAN1 = 1 << 25,
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STM32F4X_CLOCK_ENABLE_CAN2 = 1 << 26,
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STM32F4X_CLOCK_ENABLE_PWR = 1 << 28,
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STM32F4X_CLOCK_ENABLE_DAC = 1 << 29,
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STM32F4X_CLOCK_ENABLE_UART7 = 1 << 30,
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STM32F4X_CLOCK_ENABLE_UART8 = 1 << 31,
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};
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/* APB2 pins */
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enum {
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STM32F4X_CLOCK_ENABLE_TIM1 = 1 << 0,
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STM32F4X_CLOCK_ENABLE_TIM8 = 1 << 1,
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STM32F4X_CLOCK_ENABLE_USART1 = 1 << 4,
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STM32F4X_CLOCK_ENABLE_USART6 = 1 << 5,
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STM32F4X_CLOCK_ENABLE_ADC = 1 << 8,
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STM32F4X_CLOCK_ENABLE_SDIO = 1 << 11,
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STM32F4X_CLOCK_ENABLE_SPI1 = 1 << 12,
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STM32F4X_CLOCK_ENABLE_SPI4 = 1 << 13,
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STM32F4X_CLOCK_ENABLE_SYSCFG = 1 << 14,
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STM32F4X_CLOCK_ENABLE_TIM9 = 1 << 16,
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STM32F4X_CLOCK_ENABLE_TIM10 = 1 << 17,
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STM32F4X_CLOCK_ENABLE_TIM11 = 1 << 18,
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STM32F4X_CLOCK_ENABLE_SPI5 = 1 << 20,
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STM32F4X_CLOCK_ENABLE_SPI6 = 1 << 21,
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STM32F4X_CLOCK_ENABLE_SAI1 = 1 << 22,
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STM32F4X_CLOCK_ENABLE_LTDC = 1 << 26,
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STM32F4X_CLOCK_ENABLE_DSI = 1 << 27,
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};
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struct stm32f4x_pclken {
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uint32_t bus;
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uint32_t enr;
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};
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#endif /* _STM32F4_CLOCK_CONTROL_H_ */
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