zephyr/drivers/pinctrl
Manimaran A f8c8ee65be drivers: pinctrl: Microchip XEC PINCTRL glitch fix
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-05-16 18:52:44 -04:00
..
CMakeLists.txt
common.c
Kconfig
Kconfig.b91
Kconfig.cc13xx_cc26xx
Kconfig.esp32
Kconfig.gd32
Kconfig.gecko
Kconfig.ifx_cat1
Kconfig.imx
Kconfig.it8xxx2
Kconfig.kinetis
Kconfig.lpc_iocon
Kconfig.npcx
Kconfig.nrf
Kconfig.numicro
Kconfig.nxp_s32
Kconfig.rcar
Kconfig.rpi_pico
Kconfig.rv32m1
Kconfig.sam
Kconfig.sam0
Kconfig.sifive
Kconfig.smartbond
Kconfig.stm32
Kconfig.ti_k3
Kconfig.xec
Kconfig.xlnx
Kconfig.xmc4xxx
pfc_rcar.c
pinctrl_b91.c
pinctrl_cc13xx_cc26xx.c
pinctrl_esp32.c
pinctrl_gd32_af.c
pinctrl_gd32_afio.c
pinctrl_gecko.c
pinctrl_ifx_cat1.c
pinctrl_imx.c drivers: pinctrl: imx: Use sys_write32 function 2023-05-03 17:01:24 -05:00
pinctrl_ite_it8xxx2.c
pinctrl_kinetis.c
pinctrl_lpc_iocon.c
pinctrl_mchp_xec.c drivers: pinctrl: Microchip XEC PINCTRL glitch fix 2023-05-16 18:52:44 -04:00
pinctrl_npcx.c
pinctrl_nrf.c
pinctrl_numicro.c
pinctrl_nxp_s32.c
pinctrl_rpi_pico.c
pinctrl_rv32m1.c
pinctrl_sam0.c
pinctrl_sam.c
pinctrl_sifive.c
pinctrl_smartbond.c drivers: spi: Add driver for smartbond 2023-04-20 10:32:40 +02:00
pinctrl_stm32.c
pinctrl_ti_k3.c
pinctrl_xlnx_zynq.c
pinctrl_xmc4xxx.c