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zephyr/arch/xtensa/core
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Daniel Leung 9cadc8cbec xtensa: userspace: use ADDX4 to calculate syscall table index 
When looking for jump address in the syscall table, we need to
multiply the syscall ID by 4 before adding the address offset
of the beginning of the table. This is due to the jump address
being 32-bit (4 bytes). Instead of using two instructions to
shift the ID by 4 first and then the addition, we can use one
ADDX4 instruction to achieve the same result.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
..
offsets xtensa: userspace: swap page tables via assembly code 2025-04-17 00:57:19 +02:00
startup arch: xtensa: rename processor state save and restore calls 2024-10-29 07:07:42 -05:00
CMakeLists.txt xtensa: no need for flush register if threads are pin only 2025-04-17 00:57:19 +02:00
coredump.c xtensa: coredump: support dumping privilege stack 2024-09-21 11:29:39 +02:00
cpu_idle.c arch: use same syntax for custom arch calls 2024-08-12 12:43:36 +02:00
crt1.S xtensa: introduce prep_c for xtensa 2024-08-07 13:50:53 +02:00
debug_helpers_asm.S build: namespace the generated headers with zephyr/ 2024-05-28 22:03:55 +02:00
elf.c llext: avoid redundant 'ldr_parm' checks 2025-03-17 19:58:15 +01:00
fatal.c Revert "arch: deprecate _current" 2025-01-10 07:49:08 +01:00
gdbstub.c arch: define struct arch_esf and deprecate z_arch_esf_t 2024-06-04 14:02:51 -05:00
gen_vectors.py arch/xtensa: Add automatic vector linkage generation 2024-05-22 13:39:47 -05:00
gen_zsr.py xtensa: no need for flush register if threads are pin only 2025-04-17 00:57:19 +02:00
irq_manage.c xtensa: rename z_xtensa to simply xtensa 2023-12-13 09:41:24 +01:00
irq_offload.c arch: initialize irq_offload during boot, do not use SYS_INIT 2024-09-17 20:05:22 -04:00
mem_manage.c xtensa: move to use system cache API support for coherency 2024-02-03 13:42:33 -05:00
mmu.c xtensa: userspace: pre-compute MMU registers at domain init 2025-04-17 00:57:19 +02:00
mpu.c xtensa: mpu: update hardware if manipulating current domain 2024-09-16 09:55:53 +02:00
prep_c.c xtensa: no need for flush register if threads are pin only 2025-04-17 00:57:19 +02:00
ptables.c xtensa: userspace: swap page tables via assembly code 2025-04-17 00:57:19 +02:00
README_MMU.txt everywhere: replace double words 2024-06-25 06:05:35 -04:00
README_WINDOWS.rst xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
smp.c arch: call arch_smp_init() directly, do not use SYS_INIT 2024-06-12 18:23:54 -04:00
syscall_helper.c xtensa: userspace: workaround return PC calc with loops 2025-04-17 00:57:19 +02:00
thread.c xtensa: userspace: prevent potential privilege escalation 2025-04-17 00:57:19 +02:00
timing.c
tls.c
userspace.S xtensa: userspace: use ADDX4 to calculate syscall table index 2025-04-17 00:57:19 +02:00
vector_handlers.c Revert "arch: deprecate _current" 2025-01-10 07:49:08 +01:00
window_vectors.S build: namespace the generated headers with zephyr/ 2024-05-28 22:03:55 +02:00
xcc_stubs.c
xtensa_asm2_util.S xtensa: userspace: swap page tables via assembly code 2025-04-17 00:57:19 +02:00
xtensa_backtrace.c soc: xtensa/dc233c: remove xtensa_dc233c_stack_ptr_is_sane 2024-06-21 09:59:36 +02:00
xtensa_hifi.S build: namespace the generated headers with zephyr/ 2024-05-28 22:03:55 +02:00
xtensa_intgen.py arch/xtensa: xtensa_intgen.py: Emit handlers for all levels 2024-05-20 20:50:55 -04:00
xtensa_intgen.tmpl