zephyr/dts/bindings/interrupt-controller
Andriy Gelman 727e589448 drivers: interrupt_controller: Add XMC4XXX ERU driver
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.

This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.

The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-12-12 10:51:29 +01:00
..
arm,gic-v3-its.yaml
arm,gic.yaml
arm,v6m-nvic.yaml
arm,v7m-nvic.yaml
arm,v8.1m-nvic.yaml
arm,v8m-nvic.yaml
atmel,sam0-eic.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
cdns,xtensa-core-intc.yaml
cypress,psoc6-intmux-ch.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
cypress,psoc6-intmux.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
espressif,esp32-intc.yaml
gaisler,irqmp.yaml
gd,gd32-exti.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
infineon,xmc4xxx-intc.yaml drivers: interrupt_controller: Add XMC4XXX ERU driver 2022-12-12 10:51:29 +01:00
intel,ace-intc.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
intel,cavs-intc.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
intel,ioapic.yaml
intel,vt-d.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
interrupt-controller.yaml
ite,it8xxx2-intc.yaml
ite,it8xxx2-wuc-map.yaml
ite,it8xxx2-wuc.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
microchip,xec-ecia-girq.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
microchip,xec-ecia.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
mti,cpu-intc.yaml
nuclei,eclic.yaml
nuvoton,npcx-miwu-int-map.yaml dts: bindings: clean up redundant required false attributes 2022-11-20 13:12:44 -05:00
nuvoton,npcx-miwu-wui-map.yaml
nuvoton,npcx-miwu.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
nxp,s32-siul2-eirq.yaml dts: bindings: clean up redundant required false attributes 2022-11-20 13:12:44 -05:00
openisa,rv32m1-event-unit.yaml
openisa,rv32m1-intmux-ch.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
openisa,rv32m1-intmux.yaml dts: bindings: interrupt-controller: device labels are now optional 2022-07-16 16:19:17 +00:00
riscv,cpu-intc.yaml
riscv,plic0.yaml
shared-irq.yaml dts: bindings: device labels are now optional 2022-07-15 08:10:36 -05:00
sifive,plic-1.0.0.yaml
snps,archs-idu-intc.yaml
snps,arcv2-intc.yaml
snps,designware-intc.yaml
st,stm32-exti.yaml
swerv,pic.yaml
vexriscv-intc0.yaml