Dat Nguyen Duy 56cd16efbd dts: nxp: s32ze: add devicetree node for code RAM ... Add devicetree node for code RAM, code RAM can be accessed over AIXM bus or AXIF bus. Code access via AXIF interface provides the best optimal performance Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>		2024-11-26 15:43:45 -05:00
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arc/synopsys	drivers: spi: dw: define max-xfer-size	2024-01-20 13:11:42 +01:00
arm	dts: nxp: s32ze: add devicetree node for code RAM	2024-11-26 15:43:45 -05:00
arm64	dma: dma_nxp_edma: drop the hal-cfg-index property	2024-11-16 15:07:45 -05:00
bindings	dts: bindings: arm: nordic: tddconf: Add etrbuffer	2024-11-26 14:45:22 +00:00
common	dts: arm: nordic: Add power states for nRF54H20	2024-11-26 14:46:55 +00:00
nios2/intel	dts: nios2: intel: Fix unit and first address mismatch	2024-09-18 15:30:24 +02:00
posix
riscv	drivers: add the ch32v00x clock controller	2024-11-26 14:41:46 +00:00
sparc/gaisler	soc/gr716a: Enable GPIO support on LEON GR716A	2024-07-29 14:27:15 +02:00
x86/intel	dts/x86: use proper unit-address values	2024-11-18 13:18:53 -05:00
xtensa	boards: esp32xx: Use common partition tables	2024-11-22 17:45:24 +01:00
binding-template.yaml
Kconfig