Flavio Ceolin f5a0d4cd26 arch: xtensa: Optimize cache management for pinned threads ... When building with CONFIG_SCHED_CPU_MASK_PIN_ONLY we can assume that a thread will always be executed in a same CPU and consequently skip the cache invalidation. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>		2022-05-04 13:46:48 -04:00
..
core	arch/xtensa: Optimize cache management on context switch	2022-04-27 18:54:10 -04:00
include	arch: xtensa: Optimize cache management for pinned threads	2022-05-04 13:46:48 -04:00
CMakeLists.txt
Kconfig	arch/xtensa: Enable backtrace on panic on Intel ADSP platforms	2022-04-14 11:03:40 -04:00