Daniel Leung ca23a5f0cf xtensa: mmu: allow SoC to do additional MMU init steps ... This adds a function arch_xtensa_mmu_post_init() which can be implemented on the SoC layer to perform additional MMU initialization steps if necessary. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2023-08-26 16:50:40 -04:00
..
include	xtensa: mmu: rename MMU_KERNEL_RING to Z_XTENSA_KERNEL_RING...	2023-08-26 16:50:40 -04:00
offsets	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
startup
CMakeLists.txt	xtensa: mmu: Initial implementation	2023-05-23 08:54:29 +02:00
coredump.c	soc: xtensa,riscv: esp32xx: refactor folder structure	2023-07-25 18:12:33 +02:00
cpu_idle.c	xtensa: set no optimization for arch_cpu_idle() with xt-clang	2023-07-24 11:07:30 -04:00
crt1.S	xtensa: crt1: call z_xtensa_mmu_init	2023-08-26 16:50:40 -04:00
debug_helpers_asm.S	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
fatal.c	xtensa: limit speical exit() to XT_SIMULATOR	2023-05-08 09:59:54 +02:00
gdbstub.c	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
gen_zsr.py	xtensa: gen_zsr: add _STR for extra registers	2023-05-23 08:54:29 +02:00
irq_manage.c
irq_offload.c	include: add missing zephyr/irq.h include	2022-10-17 22:57:39 +09:00
README-WINDOWS.rst
timing.c
tls.c
window_vectors.S
xcc_stubs.c
xtensa_backtrace.c	soc: xtensa,riscv: esp32xx: refactor folder structure	2023-07-25 18:12:33 +02:00
xtensa_intgen.py
xtensa_intgen.tmpl
xtensa_mmu.c	xtensa: mmu: allow SoC to do additional MMU init steps	2023-08-26 16:50:40 -04:00
xtensa-asm2-util.S	xtensa: mmu: handle all data TLB misses in double exception	2023-08-26 16:50:40 -04:00
xtensa-asm2.c	xtensa: mmu: remove printing vaddr registers during exception	2023-08-26 16:50:40 -04:00