b7eb04b300
There are two set of code supporting x86_64: x86_64 using x32 ABI, and x86 long mode, and this consolidates both into one x86_64 architecture and SoC supporting truly 64-bit mode. () Removes the x86_64:x32 architecture and SoC, and replaces them with the existing x86 long mode arch and SoC. () Replace qemu_x86_64 with qemu_x86_long as qemu_x86_64. () Updates samples and tests to remove reference to qemu_x86_long. () Renames CONFIG_X86_LONGMODE to CONFIG_X86_64. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/* GCC specific test inline assembler functions and macros */
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/*
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* Copyright (c) 2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _TEST_ASM_INLINE_GCC_H
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#define _TEST_ASM_INLINE_GCC_H
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#if !defined(__GNUC__)
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#error test_asm_inline_gcc.h goes only with GCC
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#endif
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#if defined(CONFIG_X86)
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static inline void timestamp_serialize(void)
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{
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__asm__ __volatile__ (/* serialize */
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"xorl %%eax,%%eax;\n\t"
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"cpuid;\n\t"
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:
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:
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: "%eax", "%ebx", "%ecx", "%edx");
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}
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#elif defined(CONFIG_CPU_CORTEX_M)
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#include <arch/arm/cortex_m/cmsis.h>
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static inline void timestamp_serialize(void)
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{
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/* isb is available in all Cortex-M */
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__ISB();
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}
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#elif defined(CONFIG_CPU_CORTEX_R)
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#include <arch/arm/cortex_r/cpu.h>
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static inline void timestamp_serialize(void)
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{
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__ISB();
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}
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#elif defined(CONFIG_CPU_ARCV2)
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#define timestamp_serialize()
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#elif defined(CONFIG_ARCH_POSIX)
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#define timestamp_serialize()
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#elif defined(CONFIG_XTENSA)
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#define timestamp_serialize()
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#elif defined(CONFIG_NIOS2)
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#define timestamp_serialize()
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#elif defined(CONFIG_RISCV)
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#define timestamp_serialize()
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#else
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#error implementation of timestamp_serialize() not provided for your CPU target
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#endif
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#endif /* _TEST_ASM_INLINE_GCC_H */
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