Nicolas Pitre 0440a815a9 riscv: make core code 64-bit compatible ... There are two aspects to this: CPU registers are twice as big, and the load and store instructions must use the 'd' suffix instead of the 'w' one. To abstract register differences, we simply use a ulong_t instead of u32_t given that RISC-V is either ILP32 or LP64. And the relevant lw/sw instructions are replaced by LR/SR (load/store register) that get defined as either lw/sw or ld/sd. Finally a few constants to deal with register offsets are also provided. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2019-08-02 13:54:48 -07:00
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jwt.h	cleanup: include/: move zephyr/jwt.h to data/jwt.h	2019-06-27 22:55:49 -04:00
types.h	riscv: make core code 64-bit compatible	2019-08-02 13:54:48 -07:00