Daniel DeGrasse 2236eaf52c drivers: sdhc: imx_usdhc: add explicit fallthrough to I/O timing setup ... DDR50/DDR52 modes should use PINCTRL_STATE_SLOW (50MHz), so the lack of a break statement after enabling DDR mode is expected. Add an explicit __fallthrough to resolve the issue flagged by coverity scan Fixes #65324 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>		2023-12-12 10:57:20 +01:00
..
CMakeLists.txt	drivers: sdhc: added Infineon CAT1 SDHC/SDIO driver	2023-11-08 15:07:37 +00:00
ifx_cat1_sdio.c	drivers: sdhc: added Infineon CAT1 SDHC/SDIO driver	2023-11-08 15:07:37 +00:00
imx_usdhc.c	drivers: sdhc: imx_usdhc: add explicit fallthrough to I/O timing setup	2023-12-12 10:57:20 +01:00
intel_emmc_host.c	drivers: sdhc: add driver support for emmc host controller	2023-09-29 16:29:00 +02:00
intel_emmc_host.h	drivers: sdhc: add driver support for emmc host controller	2023-09-29 16:29:00 +02:00
Kconfig	drivers: sdhc: added Infineon CAT1 SDHC/SDIO driver	2023-11-08 15:07:37 +00:00
Kconfig.ifx_cat1	drivers: sdhc: added Infineon CAT1 SDHC/SDIO driver	2023-11-08 15:07:37 +00:00
Kconfig.imx
Kconfig.intel	drivers: sdhc: add driver support for emmc host controller	2023-09-29 16:29:00 +02:00
Kconfig.mcux_sdif
Kconfig.sam_hsmci
Kconfig.spi
mcux_sdif.c
sam_hsmci.c
sdhc_spi.c