f989ed949a
CLIC should be the first level interrupt controller because it replaces the basic RISC-V local interrupt. The interrupt level in CLIC controls preemption between IRQs, rather than specifying the number of nested interrupt controllers. Removed CONFIG_MULTI_LEVEL_INTERRUPTS and the incorrect interrupt level. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
30 lines
809 B
Plaintext
30 lines
809 B
Plaintext
# Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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config NUCLEI_ECLIC
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bool "Enhanced Core Local Interrupt Controller (ECLIC)"
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default y
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depends on DT_HAS_NUCLEI_ECLIC_ENABLED
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select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING if !RISCV_VECTORED_MODE
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help
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Interrupt controller for Nuclei SoC core.
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config NRFX_CLIC
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bool "VPR Core Local Interrpt Controller (CLIC)"
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default y
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depends on DT_HAS_NORDIC_NRF_CLIC_ENABLED
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select GEN_IRQ_VECTOR_TABLE
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help
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Interrupt controller for Nordic VPR cores.
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if NUCLEI_ECLIC
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config LEGACY_CLIC
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bool "Use the legacy clic specification"
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depends on RISCV_HAS_CLIC
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help
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Enables legacy clic, where smclicshv extension is not supported and
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hardware vectoring is set via mode bits of mtvec.
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endif # NUCLEI_ECLIC
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