zephyr/soc/xtensa
Andy Ross 4c54cc2221 soc/intel_adsp: Re-squash objcopy warnings
The fix for xcc build failures yesterday forgot to preserve the
squashing of stderr from the objcopy steps.  As mentioned in the
comments, there are deliberate empty sections in this link that
binutils warns about, but which are actually required, Cadence has
some vector sections in their standard exception table that don't get
populated and rimage has non-code sections that may be left empty for
non-audio-driver applications like tests.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-12-15 16:50:11 -05:00
..
esp32 debug: coredump: add xtensa coredump 2021-12-14 07:40:55 -05:00
esp32s2 soc: esp32s2: fix: data cache setup 2021-12-03 16:45:16 -06:00
intel_adsp soc/intel_adsp: Re-squash objcopy warnings 2021-12-15 16:50:11 -05:00
intel_s1000 soc/intel_s1000: Add new cAVS shim & IDC interfaces 2021-12-07 12:06:21 -05:00
nxp_adsp soc: xtensa: adsp: add support for NXP ADSP for i.MX8MP 2021-10-20 19:08:50 -04:00
sample_controller debug: coredump: add xtensa coredump 2021-12-14 07:40:55 -05:00
CMakeLists.txt soc/xtensa/intel_adsp: Upstream updates 2020-10-21 06:38:53 -04:00