Andy Ross 9eca65deca soc/intel_adsp: Correct LP-SRAM sizes in DTS ... Everything I can find as a reference says that the LP-SRAM block on these devices is 64kb, and direct experimentation with cAVS 1.5 and 2.5 agrees. Access to areas beyond 64k hangs the DSP (it should cause a PIF fault I guess, but the exception never gets trapped, that's probably a different problem). Fix this in devicetree to reflect what actually works. It's not clear where the 128k values came from; if they're not typos we can correct that when we find better docs. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2021-12-14 18:43:05 -06:00
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espressif	soc: xtensa: esp32s2: dts: uart node refactoring	2021-12-09 19:57:10 -05:00
intel	soc/intel_adsp: Correct LP-SRAM sizes in DTS	2021-12-14 18:43:05 -06:00
nxp	dts: xtensa: add device tree for imx8m	2021-10-20 19:08:50 -04:00
sample_controller.dtsi
xtensa.dtsi