Sylvio Alves 27e44acda1 clock: esp32: unify clock control for all espressif socs ... This joins all clock control handling to same source by using hal clock functions. It also brings ESP32C3 clock support. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>		2021-11-04 15:21:26 -04:00
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altr,nios2f.yaml
arm,cortex-a53.yaml	dts: bindings: cpu: fix up multi-line strings	2021-06-14 21:49:57 -04:00
arm,cortex-a72.yaml	dts: bindings: cpu: fix up multi-line strings	2021-06-14 21:49:57 -04:00
arm,cortex-m0.yaml
arm,cortex-m0+.yaml
arm,cortex-m1.yaml
arm,cortex-m3.yaml
arm,cortex-m4.yaml
arm,cortex-m4f.yaml
arm,cortex-m7.yaml
arm,cortex-m23.yaml
arm,cortex-m33.yaml
arm,cortex-m33f.yaml
arm,cortex-m.yaml
arm,cortex-r4.yaml
arm,cortex-r4f.yaml
arm,cortex-r5.yaml
arm,cortex-r5f.yaml
arm,cortex-r7.yaml
arm,cortex-r82.yaml	dts: bindings: cpu: fix up multi-line strings	2021-06-14 21:49:57 -04:00
cdns,tensilica-xtensa-lx4.yaml	dts: bindings: fix file names	2021-10-20 07:33:04 -04:00
cdns,tensilica-xtensa-lx6.yaml	dts: bindings: fix file names	2021-10-20 07:33:04 -04:00
cdns,tensilica-xtensa-lx7.yaml	dts: bindings: fix file names	2021-10-20 07:33:04 -04:00
cpu.yaml
espressif,riscv.yml	clock: esp32: unify clock control for all espressif socs	2021-11-04 15:21:26 -04:00
intel,apollo_lake.yaml
intel,atom.yaml
intel,elkhart_lake.yaml
intel,lakemont.yml
intel,x86.yaml
ite,riscv-ite.yaml	ITE: dts: cpu/yaml: fix the name of compatible	2021-10-07 06:09:45 -05:00
neorv32-cpu.yaml	soc: riscv: privilege: add neorv32 processor suppport	2021-10-15 09:46:53 -04:00
qemu,nios2-zephyr.yaml
sample_controller.yaml
snps,arcem.yaml
telink,b91.yaml	dts: riscv: add basic dts support for new Telink B91 platform	2021-07-21 05:37:12 -04:00